• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1169-1172
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.2
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• pp.305-311
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• 2010

iATA (Internet Advanced Technology Attachment) is a block-level protocol developed to transfer ATA commands over TCP/IP network, as an alternative network storage solution to address insufficient storage problem in mobile devices. This paper employs RAID5 distributed storage servers concept into iATA, in which the idea behind is to combine several machines with relatively inexpensive disk drives into a server array that works as a single virtual storage device, thus increasing the reliability and speed of operations. In the case of one machine failed, the server array will not destroy immediately but able to function in a degradation mode. Meanwhile, information can be easily recovered by using boolean exclusive OR (XOR) logical function with the bit information on the remaining machines. We perform I/O measurement and benchmark tool result indicates that additional fault tolerance feature does not delay read/write operations with reasonable file size ranged in 4KB-2MB, yet higher data integrity objective is achieved.

• Journal of the Korea Convergence Society
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• v.10 no.12
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• pp.29-34
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• 2019

If it takes much time to calculate the fitness of the solution in genetic algorithms, it is essential to create a metamodel. Much research has been completed to improve the performance of metamodels. In this study, we tried to get a better performance of metamotel using discrete Walsh transform in discrete domain. We transforms the basis of the solution and creates a metamodel using the transformed solution. We experimented with NK-landscape, a representative function of the pseudo-boolean function, and provided empirical evidence on the performance of the proposed model. When we performed the genetic algorithm using the proposed model, we confirmed that the genetic algorithm found a better solution. In particular, our metamodel showed better performance than that using the radial basis function network that modified the similarity function for the discrete domain.

• Journal of the Korea Society of Computer and Information
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• v.10 no.2 s.34
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• pp.49-57
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• 2005

In this paper. a CLB-based CPLD low power technology mapping algorithm for trade-off is proposed. To perform low power technology mapping for CPLD, a given Boolean network has to be represented to DAG. The proposed algorithm consists of three step. In the first step, TD(Transition Density) calculation have to be Performed. Total power consumption is obtained by calculating switching activity of each nodes in a DAG. In the second step, the feasible clusters are generated by considering the following conditions : the number of output. the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. The proposed algorithm is examined by using benchmarks in SIS. In the case that the number of OR-terms is 5, the experiments results show reduction in the power consumption by 30.73$\%$ comparing with that of TEMPLA, and 17.11$\%$ comparing with that of PLAmap respectively