• Title/Summary/Keyword: Boolean Algebra

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RINGS IN WHICH SUMS OF d-IDEALS ARE d-IDEALS

  • Dube, Themba
    • Journal of the Korean Mathematical Society
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    • v.56 no.2
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    • pp.539-558
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    • 2019
  • An ideal of a commutative ring is called a d-ideal if it contains the annihilator of the annihilator of each of its elements. Denote by DId(A) the lattice of d-ideals of a ring A. We prove that, as in the case of f-rings, DId(A) is an algebraic frame. Call a ring homomorphism "compatible" if it maps equally annihilated elements in its domain to equally annihilated elements in the codomain. Denote by $SdRng_c$ the category whose objects are rings in which the sum of two d-ideals is a d-ideal, and whose morphisms are compatible ring homomorphisms. We show that $DId:\;SdRng_c{\rightarrow}CohFrm$ is a functor (CohFrm is the category of coherent frames with coherent maps), and we construct a natural transformation $RId{\rightarrow}DId$, in a most natural way, where RId is the functor that sends a ring to its frame of radical ideals. We prove that a ring A is a Baer ring if and only if it belongs to the category $SdRng_c$ and DId(A) is isomorphic to the frame of ideals of the Boolean algebra of idempotents of A. We end by showing that the category $SdRng_c$ has finite products.

The application of fuzzy spatial overlay method to the site selection using GSIS (GSIS를 이용한 입지선정에 있어 퍼지공간중첩기법의 적용에 관한 연구)

  • 임승현;조기성
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.17 no.2
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    • pp.177-187
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    • 1999
  • Up to date, in many application fields of GSIS, we usually have used vector-based spatial overlay or grid-based spatial algebra for extraction and analysis of spatial data. But, because these methods are based on traditional crisp set, concept which is used these methods. shows that many kinds of spatial data are partitioned with sharp boundary. That is not agree with spatial distribution pattern of data in the real world. Therefore, it has a error that a region or object is restricted within only one attribution (One-Entity-one-value). In this study, for improving previous methods that deal with spatial data based on crisp set, we are suggested to apply into spatial overlay process the concept of fuzzy set which is good for expressing the boundary vagueness or ambiguity of spatial data. two methods be given. First method is a fuzzy interval partition by fuzzy subsets in case of spatially continuous data, and second method is fuzzy boundary set applied on categorical data. with a case study to get a land suitability map for the development site selection of new town, we compared results between Boolean analysis method and fuzzy spatial overlay method. And as a result, we could find out that suitability map using fuzzy spatial overlay method provide more reasonable information about development site of new town, and is more adequate type in the aspect of presentation.

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A Study on the Constructions of Fire Events Probabilistic Safety Assessment Model for Nuclear Power Plants (원자력발전소의 화재사건 확률론적안전성평가 모델 구축에 관한 연구)

  • Kang, Dae Il;Kim, Kilyoo
    • Journal of the Korean Society of Safety
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    • v.31 no.5
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    • pp.187-194
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    • 2016
  • A single fire event within a fire area can cause multiple initiating events considered in internal events probabilistic safety assessment (PSA). For an example, a fire event in turbine building fire area can cause a loss of the main feed-water and loss of off-site power initiating events. This fire initiating event could result in special plant responses beyond the scope of the internal events PSA model. One approach to address a fire initiating event is to develop a specific fire event tree. However, the development of a specific fire event tree is difficult since the number of fire event trees may be several hundreds or more. Thus, internal fire events PSA model has been generally constructed by modifications of the pre-developed internal events PSA model. New accident sequence logics not covered in the internal events PSA model are separately developed to incorporate them into the fire PSA model. Recently, many fire PSA models have fire induced initiating event fault trees not shown in an internal event PSA model. Up to now, there has been no analytical comparative study on the constructions of fire events PSA model using internal events PSA model with and without fault trees of initiating events. In this study, the changing process of internal events PSA model to fire events PSA model is analytically presented and discussed.

Logic Substitution Using Addition and Revision of Terms (항추가 및 보정을 적용한 대입에 의한 논리식 간략화)

  • Kwon, Oh-Hyeong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.8
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    • pp.361-366
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    • 2017
  • For two given logical expressions and, when expression contains the same part of the logical expression as expression, substituting for that part of expression is called a substituted logic expression. If a substituted relation is established between the logical expressions, there is an advantage in that the number of literals used in the whole logical expression can be greatly reduced. However, if the substituted relation is not established, there is no simplification effect obtained from the substituted expression. Previous methods proposed a way to find substituted relations between logical expressions for the given logical expressions themselves, and to calculate substituted expressions if only substitution is possible. In this paper, a new method for performing substitution with addition and revision of logic terms is proposed in order to perform substitution, even though there is no substituted relation between two logic expressions. The proposed method is efficiently implemented using a matrix that finds terms to be added. Then, by covering the matrix that has added terms, substituted logic expressions are found. Experiment results show that the proposed method for several benchmark circuits can reduce the number of literals, compared to existing synthesis tools.

Common Logic Extraction Using Hamming Distance 3 Cubes (해밍거리가 3인 큐브를 활용한 공통식 추출)

  • Kwon, Oh-Hyeong
    • The Journal of Korean Association of Computer Education
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    • v.20 no.4
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    • pp.77-84
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    • 2017
  • This paper proposes a tool that can be used as a logical expression simplification tool that can be used for deepening learning of logic circuits and further utilized as a design automation tool for optimizing semiconductor parts. The simplification method of logical expressions proposed in this paper is to find common subexpressions existing in various logical expressions and reduce the repetitive use. Finally, the goal is to minimize the number of literals used in all logical expressions. These previous studies failed to produce a common subexpression embedded in the logical expressions because they only use division principle. The proposed method uses cubes with a Hamming distance of 3 to find the common subexpression embedded between logical expressions. Experiments using benchmark circuits show that the proposed method reduces the number of literals by as much as 47% when comparing simplifications with other methods.

Incremental Techniques for Timing Analysis Considering Timing and Circuit Structure Changes (지연시간과 회로 구조 변화를 고려한 증가적 타이밍 분석)

  • O, Jang-Uk;Han, Chang-Ho
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.8
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    • pp.2204-2212
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    • 1999
  • In this paper, we present techniques which perform incremental timing analysis using Timed Boolean Algebra that solves the false path problem and extracts the timing information in combinational circuits. Our algorithm sets histories of internal inputs that are substituted for internal output and extracts maximal delays through checking sensitizability of primary outputs. Once finding the sum of primitive delay terms, then it applies modified delay with referencing histories of primary output and it can extract maximal delays of primary outputs fast and efficiently. When the structure of circuit is changed, there is no need to compute the whole circuit again. We can process partial timing analysis of computing on the gates that are need to compute again. These incremental timing analysis methods are considered both delay changes and structure of circuit, and can reduce the costs of a trial error in the circuit design.

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