• Title/Summary/Keyword: Bonding layer

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Penetration Mechanisms of Ceramic Composite Armor Made of Alumina/GFRP

  • Jung, Woo-Kyun;Lee, Hee-Sub;Jung, Jae-Won;Ahn, Sung-Hoon;Lee, Woo-Il;Kim, Hee-Jae;Kwon, Jeong-Won
    • International Journal of Precision Engineering and Manufacturing
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    • v.8 no.4
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    • pp.38-44
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    • 2007
  • Combat vehicles are frequently maneuvered in battlefields when the lives of combatants are being threatened. These vehicles are important elements that influence the consequences of a battle. Their armor must be lightweight and provide excellent protection to ensure successful operations. Ceramic composite armor has recently been developed by many countries to fulfill these requirements. We reviewed previous research to determine an effective armor design, and then fabricated a composite armor structure using $Al_2O_3$ and glass fiber-reinforced polymer. Specimens were manufactured under controlled conditions using different backing plate thicknesses and bonding methods for the ceramic layer and the backing plate. The penetration of an armor-piercing bullet was evaluated from ballistic protection tests. The bonding method between the ceramic layer and the fiber-reinforced polymer influenced the ballistic protection performance. A bonding layer using rubber provided the best protection.

A Magneto-Optic Waveguide Isolator Using Multimode Interference Effect

  • Yang, J.S.;Roh, J.W.;Lee, W.Y.;Ok, S.H.;Woo, D.H.;Byun, Y.T.;Jhon, Y.M.;Mizumoto T.;Lee,S.
    • Journal of Magnetics
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    • v.10 no.2
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    • pp.41-43
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    • 2005
  • We have investigated an optical waveguide isolator with a multimode interference section by wafer direct bonding, operating at a wavelength $1.55\;{\mu}m$. In order to fabricate the device for monolithic integration, the wafer direct bonding between a magnetic garnet material as a cladding layer and a semiconductor guiding layer has been achieved. We found that wafer direct bonding between InP and GGG $(Gd_3Ga_5O_{12})$ is effective for the integration of a waveguide optical isolator. The isolation ratio was obtained to be 2.9 dB in the device.

The Low Height Looping Technology for Multi-chip Package in Wire Bonder (와이어 본더에서의 초저 루프 기술)

  • Kwak, Byung-Kil;Park, Young-Min;Kook, Sung-June
    • Journal of the Semiconductor & Display Technology
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    • v.6 no.1 s.18
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    • pp.17-22
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    • 2007
  • Recent new packages such as MCP(Multi-Chip Package), QDP(Quadratic Die Package) and DDP(Dual Die Package) have stack type configuration. This kind of multi-layer package is thicker than single layer package. So there is need for the low height looping technology in wirebonder to make these packages thinner. There is stiff zone above ball in wirebonder wire which is called HAZ(Heat Affect Zone). When making low height loop (below $80\;{\mu}m$) with traditional forward loop, stiff wire in HAZ(Heat Affected Zone) above ball is bended and weakened. So the traditional forward looping method cannot be applied to low height loop. SSB(stand-off stitch) wire bonding method was applied to many packages which require very low loops. The drawback of SSB method is making frequent errors at making ball, neck damage above ball on lead and the weakness of ball bonding on lead. The alternative looping method is BNL(ball neckless) looping technology which is already applied to some package(DDP, QDP). The advantage of this method is faster in bonding process and making little errors in wire bonding compared with SSB method. This paper presents the result of BNL looping technology applied in assembly house and several issues related to low loop height consistence and BNL zone weakness.

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Analysis of thermal characteristic variations in LD arrays packaged by flip-chip solder-bump bonding technique (플립 칩 본딩으로 패키징한 레이저 다이오우드 어레이의 열적 특성 변화 분석)

  • 서종화;정종민;지윤규
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.3
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    • pp.140-151
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    • 1996
  • In this paper, we analyze the variations of thermal characteristics of LD (laser diode) arrays packaged by a flip-chip bonding method. When we simulate the temperature distribution in LD arrays with a BEM (boundary element method) program coded in this paper, we find that thermal crosstalks in LD arrays packaged by the flip-chip bonding method increases by 250-340% compared to that in LD arrays packaged by previous methods. In the LD array module packaged by the flip-chip bonding technique without TEC (thermo-electric cooler), the important parameter is the absolute temperature of the active layer increased due cooler), the important parameter is the absolute temperature of th eactiv elayers of LD arrays to thermal crosstalk. And we find that the temperature of the active layers of LD arrays increases up to 125$^{\circ}C$ whenall four LDs, without a carefully designed heatsink, are turned on, assuming the power consumption of 100mW from each LD. In order to reduce thermal crosstalk we propose a heatsink sturcture which can decrease the temeprature at the active layer by 40%.

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Microstructure Evolution and Mechanical Properties of Wire-Brushed Surface and Roll-Bonded Interface of Aluminum Sheets (와이어 브러싱한 알루미늄 판재 표면 및 압연접합 계면의 미세조직 및 기계적 성질)

  • Kim, Su-Hyeon;Kim, Hyoung-Wook;Kang, Joo-Hee;Euh, Kwangjun
    • Korean Journal of Metals and Materials
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    • v.49 no.5
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    • pp.380-387
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    • 2011
  • Wire brushing, which is a typical surface preparation method for roll bonding, has recently been highlighted as a potentially effective method for surface nanocrystallization. In the present study, the microstructure evolution and hardness of the wire-brushed surface and roll-bonded interface of a 1050 aluminum sheet were investigated. Wire brushing formed protruded layers with a nanocrystalline structure and extremely high surface hardness. After roll bonding, the protruded layers remained as hard layers at the interface. Due to their hardness and brittleness the interface hard layers, can affect the interface bonding properties and also play an important role determining the mechanical properties of multi-layered clad sheets.

Temperature Distribution According to the Structure of a Conductive Layer during Joule-heating Induced Encapsulation for Fabrication of OLED Devices (OLED 소자 제조를 위한 주울 가열 봉지 공정 시 도전층 구조에 따르는 열분포)

  • Jang, Ingoo;Ro, Jae-Sang
    • Journal of the Korean institute of surface engineering
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    • v.46 no.4
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    • pp.162-167
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    • 2013
  • Encapsulation is required since organic materials used in OLED devices are fragile to water vapor and oxygen. Laser sealing method is currently used where IR laser is scanned along the glass-frit coated lines. Laser method is, however, not suitable to encapsulating large-sized glass substrate due to the nature of sequential scanning. In this work we propose a new method of encapsulation using Joule heating. Conductive layer is patterned along the sealing lines on which the glass frit is screen printed and sintered. Electric field is then applied to the conductive layer resulting in bonding both the panel glass and the encapsulation glass by melting glass-frit. In order to obtain uniform bonding the temperature of a conductive layer having a shape of closed loop should be uniform. In this work we conducted simulation for heat distribution according to the structure of a conductive layer used as a Joule-heat source. Uniform temperature was obtained with an error of 5% by optimizing the structure of a conductive layer. Based on the results of thermal simulations we concluded that Joule-heating induced encapsulation would be a good candidate for encapsulation method especially for large area glass substrate.

Fluxless Bonding Method between Sn and In Bumps Using Ag Capping Layer (Ag층을 이용한 Sn과 In의 무 플럭스 접합)

  • Lee Seung-Hyun;Kim Young-Ho
    • Journal of the Microelectronics and Packaging Society
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    • v.11 no.2 s.31
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    • pp.23-28
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    • 2004
  • We utilized Ag capping layer for fluxless bonding. To investigate the effect of Ag capping layer, two sets of sample were used. One set was bare In and Sn solders. The other set was In and Sn solders with Ag capping layer. In ($10{\mu}m$) and Sn ($10{\mu}m$) solders were deposited on Cu/Ti/Si substrate using thermal-evaporation, and Ag ($0.1{\mu}m$) capping layers were deposited on In and Sn solders. Solder joints were made by joining two In and Sn deposited specimens at $130^{\circ}C$ for 30 s under 0.8, 1.6, 3.2 MPa using thermal compression bonder. The contact resistance was measured using four-point probe method. The shear strength of the solder joints was measured by the shear test of cross-bar sample in the direction. The microstructure of the solder joints was characterized with SEM and EDS. In and Sn solders without Ag capping layers were only bonded at $130^{\circ}C$ under high bonding pressure. Also the shear strength of the In-Sn solder joints under was lower than that of the Ag/In-Ag/Sn solder joints. The resistance of the solder joints was $2-4\;m{\Omega}$ The solder joints consisted of In-rich phase and Sn-rich phase and the intermixed compounds were found at the interface. As bonding pressure increased, the intermixed compounds formed more.

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Transient Liquid Phase (TLP) Bonding of Device for High Temperature Operation (고온동작소자의 패키징을 위한 천이액상확산접합 기술)

  • Jung, Do-hyun;Roh, Myung-hwan;Lee, Jun-hyeong;Kim, Kyung-heum;Jung, Jae Pil
    • Journal of the Microelectronics and Packaging Society
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    • v.24 no.1
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    • pp.17-25
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    • 2017
  • Recently, research and application for a power module have been actively studied according to the increasing demand for the production of vehicles, smartphones and semiconductor devices. The power modules based on the transient liquid phase (TLP) technology for bonding of power semiconductor devices have been introduced in this paper. The TLP bonding has been widely used in semiconductor packaging industry due to inhibiting conventional Pb-base solder by the regulation of end of life vehicle (ELV) and restriction of hazardous substances (RoHS). In TLP bonding, the melting temperature of a joint layer becomes higher than bonding temperature and it is cost-effective technology than conventional Ag sintering process. In this paper, a variety of TLP bonding technologies and their characteristics for bonding of power module have been described.

Vibration Characteristics of a Wire-Bonding Piezoelectric Actuator (와이어 본딩용 압전 액츄에이터의 진동 특성)

  • Kim, Young-Woo;Kim, Kyoung-Up;Lee, Seung-Yop
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2007.11a
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    • pp.578-582
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    • 2007
  • In this paper, vibration modes and frequencies of a ring-type stacked piezoelectric actuator for a wire bonding transducer system are analyzed using FEM simulations. We implement experiments using a commercial product model of the actuator PZT module which consists of 6 layer ring-type PZT and 7 electrodes, combined bolts, nut and tinut. There are two main results: One is that FEM analysis should consider the effect the harmonic voltage input in order to meet the experimental results. The other is that the current wire bonder using exciting frequency of 136 kHz should be modified in order to improve the actuator and bonding performance because the actuator module has the main longitudinal mode of 145 kHz.

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Glass to Metal Bonding by Electric Field (전장에 의한 유리와 금속의 접합)

  • 정우창;김종희
    • Journal of the Korean Ceramic Society
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    • v.20 no.1
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    • pp.70-78
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    • 1983
  • This paper discusses the application of Si-Borosilicate glass sealing to a new sealing method which utilizes a large electrostatic field to pormote bound formation at relatively low temperature. Bonding mechanism and the effect of bonding time bonding temperature glass thickness and surface roughness on the bond strength were investigated. Application of a de voltage across bonded specimen gradually produced a layer of glass adjacent silicon which was depleted of mobile ions. As a consequence a n increasingly larger fraction of the applied voltage appeared across the depleted region and very large electric field resulted This field accompanyed by large electrostatic force acted as driving force the of strong bond. And stronger bond was formed with increasing bonding time and temperature. A low temperature preoxidation is advantageous for the Si surface having a rougher surface finish that 1 microinch.

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