• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.32-39
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• 1989

This paper presents Lucifer-type encryption algorythms with variable length of block size of 32, 64, and 256 bits by varying the key byte access schedule and the unfolded convolution register of Lucifer. The intersymbol dpendence and exhaustive cryptanalysis of the algorithms are examined and compared. We also present the methods which improve the intersymbol dependence such as moving the location of key interruption and autoclave selection of S-box.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.4
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• pp.119-125
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• 2013

The amount of digital content grows exponentially by the development of the internet and the change of computing environments and the target also is getting wider. The industry using this digital content has been growing greatly. However, the distribution of pirated digital content is increasing using internet because digital content is easy to store and transmit and the damage is growing. In this paper, we propose safety trading system which can conceal the author's information safely in digital content in order to block illegal distribution of digital content. ARIA encryption algorithm is used to protect the concealed information of author in digital content and it is a help to track the illegal traders by doing fingerprinting of buyer information to digital content and managing the transaction information. The technical support for copyright dispute is to allow by providing the capability to verify illegal edit to original digital contents.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.253-255
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• 2017

본 논문에서는 IoT 디바이스의 인증암호를 위한 AES-GCM 암호코어를 설계하였다. AES-GCM 코어는 블록암호 AES와 GHASH 연산으로 기밀성과 무결성을 동시에 제공한다. 기밀성 제공을 위한 블록암호 AES는 운영모드 CTR과 비밀키 길이 128/256-bit를 지원한다. GHASH 연산과 AES 암호화(복호화)의 병렬 동작을 위해 소요 클록 사이클을 일치시켜 GCM 동작을 최적화 하였다. 본 논문에서는 AES-GCM 코어를 Verilog HDL로 모델링 하였고 ModelSim을 이용한 시뮬레이션 검증 결과 정상 동작함을 확인하였으며 Xilinx Virtex5 XC5VSX95T FPGA 디바이스 합성결과 4,567 슬라이스로 구현되었다.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.3
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• pp.9-17
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• 2012

In this paper, we propose a SPN 256 bit block cipher so called XSB(eXtended SPN Block cipher) which has a symmetric structure in encryption and decryption. The proposed XSB is composed of the even numbers of N rounds where the first half of them, 1 to N/2-1 round, applies a pre-function and the last half of them, N/2+1 to N round, employs a post-function. Each round consists of a round key addition layer, a substiution layer, a byte exchange layer and a diffusion layer. And a symmetry layer is located in between the pre-function layer and the post-function layer. The symmetric layer is composed with a multiple simple bit slice involution S-Boxes. The bit slice involution S-Box symmetric layer increases difficult to attack cipher by Square attack, Boomerang attack, Impossible differentials cryptanalysis etc.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.143-151
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• 2011

Plaintext and key are independent in the existing block cipher. Also, encryption/decryption is performed by using structural features. Therefore, the external environment of suggested mixed cryptographic algorithm is identical with the existing ones, but internally, features of the existing block cipher were meant to be removed by making plaintext and key into dependent functions. Also, to decrease the loads on the authentication process, authentication add-on with dependent characteristic was included to increase the use of symmetric cryptographic algorithm. Through the simulation where the proposed cryptosystem was implemented in the chip level, we show that our system using the shorter key length than the length of the plaintext is two times faster than the existing systems.

• Journal of Information Processing Systems
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• v.8 no.1
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• pp.159-174
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• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.

• Journal of Korea Society of Industrial Information Systems
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• v.25 no.5
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• pp.13-21
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• 2020

This paper proposes a sign reversal channel switching method in space-frequency block code for orthogonal frequency division multiplexing system. In case of sending source data on other antenna, it is necessary for the receiver to change combining method according to the channel variation. If one does not know the predefined channel switching sequence, it is not possible to decode the received data precisely. In transmit data symbols' exchanges for a channel switching, data symbols are exchanged according to a format of space-frequency block code. In this paper, we proposes a simple sign reversal method except exchanging data symbols between transmit antennas. It is shown that this method occurs another combining method for a simple encryption in the receiver.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.285-287
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• 2014

This paper describes a design of area-efficient/low-power cryptographic processor for lightweight block cipher algorithm HIGHT which was approved as a cryptographic standard by KATS and ISO/IEC. The HIGHT algorithm which is suitable for the security of IoT(Internet of Things), encrypts a 64-bit plain text with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we adopt 32-bit data path and optimize round transform block and key scheduler to share hardware resources for encryption and decryption.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.1
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• pp.435-451
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• 2019

Impossible differential cryptanalysis is an essential cryptanalytic technique and its key point is whether there is an impossible differential path. The main factor of influencing impossible differential cryptanalysis is the length of the rounds of the impossible differential trail because the attack will be more close to the real encryption algorithm with the number becoming longer. We provide the upper bound of the longest impossible differential trails of several important block ciphers. We first analyse the national standard of the Russian Federation in 2015, Kuznyechik, which utilizes the 16-byte LFSR to achieve the linear transformation. We conclude that there is no any 3-round impossible differential trail of the Kuznyechik without the consideration of the specific S-boxes. Then we ascertain the longest impossible differential paths of several other important block ciphers by using the matrix method which can be extended to many other block ciphers. As a result, we show that, unless considering the details of the S-boxes, there is no any more than or equal to 5-round, 7-round and 9-round impossible differential paths for KLEIN, Midori64 and MIBS respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.2
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• pp.221-231
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• 2013

Exchanging personal health information(PHI) is an essential process of healthcare services using information and communication technology. But the process have the inherent risk of information disclosure, so the PHI should be protected to ensure the reliability of healthcare services. In this paper, we designed encryption module for wearable personal health devices(PHD). A main goal is to guarantee that the real-time encoded and transmitted PHI cannot be allowed to be read, revised and utilized without user's permission. To achieve this, encryption algorithms as DES and 3DES were implemented in modules operating in Telos Rev B(16bit RISC, 8Mhz). And the experiments were performed in order to evaluate the performance of encryption and decryption using vital-sign measured by PHD. As experimental results, an block encryption was measured the followings: DES required 1.802 ms and 3DES required 6.683 ms. Also, we verified the interoperability among heterogeneous devices by testing that the encrypted data in Telos could be decoded in other machines without errors. In conclusion, the encryption module is the method that a PHD user is given the powerful right to decide for authority of accessing his PHI, so it is expected to contribute the trusted healthcare service distribution.