• Journal of IKEEE
• /
• v.22 no.1
• /
• pp.38-45
• /
• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2021.10a
• /
• pp.229-231
• /
• 2021

In this paper, we describe a hardware design of the SIMECK block cipher algorithm that can be implemented in lightweight hardware with appropriate security strength. To achieve fast encryption and decryption operations, it was designed using two-step method that reduces the number of operation rounds. The designed SIMECK cryptographic core was implemented in Arty S7-50 FPGA device and its hardware operation was verified with a GUI using Python.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.786-792
• /
• 2016

Camellia was jointly developed by Nippon Telegraph and Telephone Corporation and Mitsubishi Electric Corporation in 2000. Camellia specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, a modified round operation block which unifies a register setting for key schedule and a conventional round operation block is proposed. 16 ROMs needed for key generation and round operation are implemented using only 4 dual-port ROMs. Due to the use of a message buffer, encryption/decryption can be executed without a waiting time immediately after KA and KB are calculated. The suggested block cipher Camellia algorithm is designed using Verilog-HDL, implemented on Virtex4 device and operates at 184.898MHz. The designed cryptographic core has a maximum throughput of 1.183Gbps in 128-bit key mode and that of 876.5Mbps in 192 and 256-bit key modes. The cryptographic core of this paper is applicable to security module of the areas such as smart card, internet banking, e-commerce and satellite broadcasting.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.4C
• /
• pp.356-364
• /
• 2003

Presently, etwork is being in the existence as an influence can not be neglected. This rapid progress of network has gone with development of mobile network and information communication. But the development of network can generate serous social problems. So, it is highly required to control security of network. These problems related security will be developed and keep up to confront with anti-security part such as hacking, cracking. There's no way to preserve security from hacker or cracker without delvelopping new cryptographic algorithm or keeping the state of anti-cryptanalysis in a prescribed time by means of extendig key-length. Worldwidely, many researchers for network security are trying to handle these problems. In this paper, we proposed a new block cryptosystem. The Block cipher-Secure Electronic Xenogenesis Algorithm(B-SEXA) which is capable to cipher regardless of key distribution or key-length for these definite problem is proposed and designed in hardware. B-SEXA increase secret level from using a MDP and MLP in maximum is proposed to prevent cryptograpy analysis. The designed B-SEXA in this paper performed synthesization and simulation using Synopsys Vwe. 1999.10 and VHDL.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.6
• /
• pp.1075-1082
• /
• 2017

This paper describes a design of hash processor which can execute new hash algorithm, SHA-3 and extendable-output function (XOF), SHAKE-256. The processor that consists of padder block, round-core block and output block maximizes its performance by using the block-level pipelining scheme. The padder block formats the variable-length input data into multiple blocks and then round block generates SHA-3 message digest or SHAKE256 result for multiple blocks using on-the-fly round constant generator. The output block finally transfers the result to host processor. The hash processor that is implemented with Xilinx Virtex-5 FPGA can operate up to 220-MHz clock frequency. The estimated maximum throughput is 5.28 Gbps(giga bits per second) for SHA3-512. Because the processor supports both SHA-3 hash algorithm and SHAKE256 algorithm, it can be applicable to cryptographic areas such as data integrity, key generation and random number generation.

• Journal of the Korea Society for Simulation
• /
• v.9 no.2
• /
• pp.15-25
• /
• 2000

Since data security problems are very important in the information age, cryptographic algorithms for encryption and decryption have been studied for a long time. The GOST(Gosudarstvennyi Standard or Government Standard) algorithm as a data encryption algorithm with a 256-bit key is a 64-bit block algorithm developed in the former Soviet Union. In this paper, we describe how to design an encryption chip based on the GOST algorithm. In addition, the GOST algorithm is compared with the DES(Data Encryption Standard) algorithm, which has been used as a conventional data encryption algorithm, in modeling techniques and their performance. The GOST algorithm whose key size is relatively longer than that of the DES algorithm has been expanded to get better performance, modeled in VHDL, and simulated for implementation with an CPLD chip.

• Journal of Internet Computing and Services
• /
• v.21 no.3
• /
• pp.11-19
• /
• 2020

In this paper, a merged TEA block cipher processor which unifies Tiny Encryption Algorithm(TEA), extended Tiny Encryption Algorithm(XTEA) and corrected block TEA(XXTEA) is designed. After TEA cipher algorithm was first designed, XTEA and XXTEA cipher algorithms were designed to correct security weakness. Three types of cipher algorithm uses a 128-bit master key. The designed cipher processor can encrypt or decrypt 64-bit message block for TEA/XTEA and variable-length message blocks up to 256-bit for XXTEA. The maximum throughput for 64-bit message blocks is 137Mbps and that of 256-bit message blocks is 369Mbps. The merged TEA block cipher designed in this paper has a 16% gain on the area side compared to a lightweight LEA cipher. The cryptographic IP of this paper is applicable in security module of the mobile areas such as smart card, internet banking, and e-commerce.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.125-128
• /
• 2011

This paper describes an efficient hardware implementation of HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a $0.35-{\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.164-167
• /
• 2002

This paper presents the design of Rijndael crypto-processor with 128 bits, 192 bits and 256 bits key size. In October 2000 Rijndael cryptographic algorithm is selected as AES(Advanced Encryption Standard) by NIST(National Institute of Standards and Technology). Rijndael algorithm is strong in any known attacks. And it can be efficiently implemented in both hardware and software. We implement Rijndael algorithm in hardware, because hardware implementation gives more fast encryptioN/decryption speed and more physically secure. We implemented Rijndael algorithm for 128 bits, 192 bits and 256 bits key size with VHDL, synthesized with Synopsys, and simulated with ModelSim. This crypto-processor is implemented using on-the-fly key generation method and using lookup table for S-box/SI-box. And the order of Inverse Shift Row operation and Inverse Substitution operation is exchanged in decryption round operation of Rijndael algorithm. It brings about decrease of the total gate count. Crypto-processor implemented in these methods is applied to mobile systems and smart cards, because it has moderate gate count and high speed.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.12
• /
• pp.4962-4967
• /
• 2010

Security of the electronic commercial transaction especially through the information communication network is gaining its significance due to rapid development of information and communication related fields. For that, some kind of cryptographic algorithm is already in use for the smart card. However, the growing needs of handling multimedia and real time communication bring the smart card into more stringent use of its resources. Therefore, we proposed a key scheduler block of the smart card to facilitate multimedia communication and real time communication.