• The Journal of the Acoustical Society of Korea
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• v.18 no.4E
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• pp.43-50
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• 1999

A fast converging coding algorithm that adaptively selects the modes of macroblocks is introduced. For a given frame, the optimal modes are selected based on the decision curves that minimize the overall distortion at a given bit rate. The method proposed in this paper is different from the conventional ones in that it does not manipulate the quantizer to meet the target bit rate but it satisfies the target bit rate by finding optimal modes of macroblocks which result consistent visual quality. Lagrange multiplier of the unconstrained cost function is controlled to trigger decision curves to generate appropriate modes to meet bit rate and the curve is obtained by utilizing simulated annealing optimization technique. The algorithm is implemented within H.261 video codec and simulation results demonstrate superior visual quality.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2032-2041
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• 1998

In this work, we propose a novel bit allocation method that is to minimize overall distortions subject ot the bit rate constraint. We partition the original bitallocation problem into 'macroblock level bit allocation' problems that can be solved by conventional Lagrangian mutiplier methods and a 'frame level bit allocation' problem. To tackle the frame level problem, 'two-phase optimization' algorithm is used with iter-frame dependency model. While the existing approaches are almost impossible to find the macroblock-unit result for the moving picture coding system due to high computational complexity, the proposed algorithm can drastically reduce the computational loads by the problem partitioning and can obtain the result close to the optimal solution. Because the optimally allocated results can be used as a benchmark for bit allocation methods, the upper performance limit, or a basis for approximation method development, we expect that the proposed algorithm can be very useful for the bit allocation related works.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.55-61
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• 2003

The Data Encryption Standard(DES) has been a worldwide standard for over 20 years. DES is one of the block encryption techniques which ciphers 64-bit input data blocks using a 56-bit private key. The DES algorithm transforms 64-bit input in a series of steps into a 64-bit output. Thus, it is impossible to deduce the plaintext from the ciphertext which encrypted by this algorithm without the key. This paper presents an implementation of RFID roader system using the DES algorithm. An implemented system enhances the credibility of the encryption algorithm by using the Cipher Block Chining(CBC). Experimental results also show that the implemented system has better performance over the conventional commercial product.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.637-647
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• 2010

This paper suggested an algorithm that uses a multiplier, 'w bit $\times$ w bit = 2w bit', to process $\frac{N}{D}$ integer division of 2w bit integer N and w bit integer D. An algorithm suggested of the research, when the divisor D is '$D=0.d{\times}2^L$, 0.5 < 0.d < 1.0', approximate value of $\frac{1}{D}$, '$1.g{\times}2^{-L}$', which satisfies '$0.d{\times}1.g=1+e$, e < $2^{-w}$', is defined as over reciprocal number and the dividend N is segmented in small word more than 'w-3' bit, and partial quotient is calculated by multiplying over reciprocal number in each segmented word, and quotient of double precision integer division is evaluated with sum of partial quotient. The algorithm suggested in this paper doesn't require additional correction, because it can calculate correct reciprocal number. In addition, this algorithm uses only multiplier, so additional hardware for division is not required to implement microprocessor. Also, it shows faster speed than the conventional SRT algorithm. In conclusion, results from this study could be used widely for implementation SOC(System on Chip) and etc. which has been restricted to microprocessor and size of the hardware.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.11 no.6
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• pp.77-87
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• 2001

This paper describes a design of cryptographic processor that implements the Rijndael cipher algorithm, the Advanced Encryption Standard algorithm. It can execute both encryption and decryption, and supports only 128-bit block and 128-bit keys. As the processor is implemented only one round, it must iterate 11 times to perform an encryption/decryption. We implemented the ByteSub and InvByteSub transformation using the algorithm for minimizing the increase of area which is caused by different encryption and decryption. It could reduce the memory size by half than implementing, with only ROM. We estimate that the cryptographic processor consists of about 15,000 gates, 32K-bit ROM and 1408-bit RAM, and has a throughput of 1.28 Gbps at 110 MHz clock based on Samsung 0.5um CMOS standard cell library. To our knowledge, this offers more reduced memory size compared to previously reported implementations with the same performance.

• The Journal of the Acoustical Society of Korea
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• v.28 no.3
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• pp.290-297
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• 2009

This paper presents an improved adaptive multi-rate wideband (AMR-WB) algorithm for the efficient Text-To-Speech (TTS) database compression. The proposed algorithm includes unnecessary common bit-stream (CBS) removal and parameter delta coding combined with speaker-dependent huffman coding to reduce the required bit-rate without any quality degradation. We also propose lossy coding schemes to produce the maximum bit-rate reduction with negligible quality degradation. The proposed lossless algorithm including CBS removal can reduce bit-rate by 12.40% without quality degradation compared with the 12.65 kbps AMR-WB mode. The proposed lossy algorithm can reduce bit-rate by 20.00% with 0.12 PESQ degradation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.436-442
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• 2014

A new bus-invert coding circuit, called Two-bit Bus-Invert Coding (TBIC) is presented. TBIC partitions a bus into a set of two-bit sub-buses, and applies the bus-invert (BI) algorithm to each sub-bus. Unlike ordinary BI circuits using invert-lines, TBIC does not use an invert-line, so that it sends coding information through a bus-line. To transmit 3-bit information with 2 bus-lines, TBIC allows one bus-line to have a mid-level state, called M-state. TBIC increases the performance of BI algorithm, by suppressing the generation of overhead transitions. TBIC reduces bus transitions by about 45.7%, which is 83% greater than the maximum achievable performance of ordinary BI with invert-lines.

• The Journal of the Korea Contents Association
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• v.3 no.2
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• pp.11-18
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• 2003

In this paper, we propose a fast variable block matching algorithm for motion estimation based on bit-patterns. Motion estimation in the proposed algorithm is peformed after the representation of image sequence is transformed 8-bit pixel values into 1-bit ones by the mean pixel value of search block, which brings a short searching time by reducing the computational complexity. Moreover, adaptive searching methods according to the motion information of the block make the procedure of motion estimation efficient by eliminating unnecessary searching processes of low motion block and deepening a searching procedure in high motion block. Experimental results show that the proposed algorithm provides bettor performance - average 0.5dB PSNR improvement and about 99% savings in the number of operations - than full search Hock matching algorithm with a fixed block size.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.543-550
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• 2000

An adaptive bit-reduced mean absolute difference (ABRMAD) is presented as a criterion for the block-matching algorithm (BMA) to reduce the complexity of the VLSI Implementation and to improve the processing time. The ABRMAD uses the lower pixel resolution of the significant bits instead of full resolution pixel values to estimate the motion vector (MV) by examining the pixels Ina block. Simulation results show that the 4-bit ABRMAD has competitive mean square error (MSE)results and a half less hardware complexity than the MAD criterion, It has also better characteristics in terms of both MSE performance and hardware complexity than the Minimax criterion and has better MSE performance than the difference pixel counting(DPC), binary block-matching with edge-map(BBME), and bit-plane matching(BPM) with the same number of bits.

• Journal of Broadcast Engineering
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• v.16 no.4
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• pp.647-656
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• 2011

Motion estimation using one-bit transform and two-bit transform reduces the complexity for computation of matching error; however, the peak signal-to-noise ratio (PSNR) is degraded. Modified 1BT (M1BT) and modified 2BT (M2BT) have been proposed to compensate degraded PSNR by adding conditional local search. However, these algorithms require many additional search points in fast moving sequences with a block size of $16{\times}16$. This paper provides more efficient search method by preparing candidate blocks using the number of non-matching points (NNMP) than the conditional local search. With this NNMP-based search, we can easily obtain candidate blocks with small NNMP and efficiently search final motion vector. Experimental results show that the proposed algorithm not only reduces computational complexity, but also improves PSNR on average compared with conventional search algorithm used in M1BT, M2BT and AM2BT.