• 전기전자학회논문지
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• 제5권1호
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• pp.43-51
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• 2001

메모리의 집적도가 올라갈수록 원치 않는 셀간의 간섭과 동시에 bit-line간의 상호 노이즈도 증가하게 된다. 그리고 높은 고장 검출율을 요구하는 고집적 메모리의 테스트는 많은 테스트 백터를 요구하게 되거나 비교적 큰 추가 테스트 회로를 요구하게 된다. 지금까지 기존의 테스트 알고리즘은 이웃 bit-line의 간섭이 아니라 이웃 셀에 중점을 두었다. 본 논문에서는 NPSFs(Neighborhood Pattern Sensitive Faults)를 기본으로 한 NBLSFs(Neighborhood Bit-Line Sensitive Faults)를 위한 새로운 테스터 알고리즘을 제안한다. 그리고 제안된 알고리즘은 부가 회로를 요구하지 않는다. 메모리 테스트를 위해 기존의 5개의 셀 레이아웃이나 9개의 셀 레이아웃을 사용하지 않고 NBLSF 검출에 최소한 크기인 3개의 셀 레이아웃을 이용하였다. 더구나 이웃 bit-line에 의한 최대의 상호잡음을 고려하기 위해 테스트 동작에 refresh 동작을 추가하였다(예 $write{\rightarrow}\;refresh{\rightarrow}\;read$). 또한 고착고장, 천이고장, 결합고장, 기존의 pattern sensitive 고장, 그리고 이웃 bit-line sensitive 고장 등도 검출될 수 있음을 보여준다.

• 한국멀티미디어학회논문지
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• 제24권8호
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• pp.1012-1019
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• 2021

Currently, since the black-white QR (Quick Response) codes have limited storage capacity, color QR codes have been actively being studied. By multiplexing 3 colors, the color QR codes can allow the code capacity to be increased by three times, however, the color multiplexing brings about the possibility of crosstalk and noises in the acquisition process of the final image, incurring the decrease of bit-recognition rate. In order to improve the bit recognition rate, while keeping the storage capacity high, this paper proposes a new type of color QR code which uses the pattern information as well as the color information, and then analyzes how to increase the bit recognition rate. For this aim, the paper presents an efficient system which extracts embedded information from color QR code and then, through practical experiments, it is shown that the proposed color QR codes improves the bit recognition rate and are useful for commercial applications, compared to the conventional color codes.

• 보존과학연구
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• 통권26호
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• pp.41-56
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• 2005

A set of horse bit from the Eonnam-ri site consists of three parts, pyo , ham , andinsu , and each part takes a shape of a piece of bar. According to current typological study, the pyo is S type, the insu is two-braided line type, and the outer rim of the ham is double rim type, respectively. According to X-ray test, inlaid design seems to have been decorated on the whole surface of the iron bit, originally. However, inlaid pattern partially remained. While the part of bit stopper is designed with flame pattern, the part of rein joint is designed with cloud pattern. According to XRF and XGT analysis of inlaid material, the content of silver is not more than 50%. The line inlay method making grooves on the surface of iron, then in laying a silver thread into them, and grinding the surface in a direction was adoptedin the manufacture of the iron bit.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제15권2호
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• pp.121-125
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• 2015

In this paper, we propose a method that extracts features from character patterns using the fractal dimension of chaos theory. The input character pattern image is converted into time-series data. Then, using the modified Henon system suggested in this paper, it determines the last features of the character pattern image after calculating the box-counting dimension, natural measure, information bit, and information (fractal) dimension. Finally, character pattern recognition is performed by statistically finding each information bit that shows the minimum difference compared with a normalized character pattern database.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2011년도 춘계학술발표대회
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• pp.346-349
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• 2011

In this paper, we design a perceptually invisible dot pattern layout and its recognition scheme, and we apply the recognition scheme into a smart self learning aid for interactive learning aid. To increase maximum information capacity and also increase robustness to the noises, we design a ECC (error correcting code) based dot pattern with directional vector indicator. To make a smart self-learning aid, we embed the micro dot pattern (20 information bit + 15 ECC bits + 9 layout information bit) using K ink (CMYK) and extract the dot pattern using IR (infrared) LED and IR filter based camera, which is embedded in the smart pen. The reason we use K ink is that K ink is a carbon based ink in nature, and carbon is easily recognized with IR even without light. After acquiring IR camera images for the dot patterns, we perform layout adjustment using the 9 layout information bit, and extract 20 information bits from 35 data bits which is composed of 20 information bits and 15 ECC bits. To embed and extract information bits, we use topology based dot pattern recognition scheme which is robust to geometric distortion which is very usual in camera based recognition scheme. Topology based pattern recognition traces next information bit symbols using topological distance measurement from the pivot information bit. We implemented and experimented with sample patterns, and it shows that we can achieve almost 99% recognition for our embedding patterns.

• 대한임베디드공학회논문지
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• 제8권5호
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• pp.285-293
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• 2013

The procedure of the arbitration which is the tag collision is essential because the multiple tags response simultaneously in the same frequency to the request of the Reader. This procedure is known as Anti-collision and it is a key technology in the RFID system. In this paper, we propose the Bit Pattern Prediction Algorithm(BPPA) for the efficient identification of the multiple tags. The BPPA is based on the tree algorithm using the time slot and identify the tag quickly and efficiently using accurate bit pattern prediction method. Through mathematical performance analysis, We proved that the BPPA is an O(n) algorithm by analyzing the worst-case time complexity and the BPPA's performance is improved compared to existing algorithms. Through MATLAB simulation experiments, we verified that the BPPA require the average 1.2 times query per one tag identification and the BPPA ensure stable performance regardless of the number of the tags.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.703-706
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• 2003

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.

• 한국시뮬레이션학회논문지
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• 제14권1호
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• ETRI Journal
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• 제26권6호
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• 융합보안논문지
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• 제14권5호
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• pp.17-24
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• 2014

본 논문에서는 얼굴 표정 인식을 위한 지역미세패턴(local micro pattern)의 하나인 LBP(Local Binary Pattern) 코드의 잡음에 대한 단점을 해결하기위하여 새로운 미세패턴 방법인 LDP(Local Directional Pattern)를 제안한다. 제안된 방법은 LBP의 문제점을 해결하기 위해 $m{\times}m$ 마스크를 이용하여 8개의 방향 성분을 구하고, 이를 크기에 따라서 정렬한 후 상위 k개를 선정하여 해당 방향을 나타내는 비트를 1로 설정한다. 그리고 8개의 방향 비트를 순차적으로 연결하여 최종 패턴 코드를 생성한다. 실험결과, 제안된 방법은 기존 방법에 비해 회전에 대한 영향이 적으며, 잡음에 대한 적응력이 현저히 높았다. 또한, 제안된 방법을 기반으로 얼굴의 영구적인 특징과 일시적인 특징을 함께 표현하는 새로운 지역미세패턴의 개발이 가능함을 확인하였다.