• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.43-51
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• 2001

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased. And testing high-density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. So far, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new test algorithm for neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs(Neighborhood Pattern Sensitive Faults) is proposed. And the proposed algorithm does not require any additional circuit. Instead of the conventional five-cell or nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. Furthermore, to consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e.,$write{\rightarrow}\;refresh{\rightarrow}\;read$). Also, we show that the proposed algorithm can detect stuck-at faults, transition faults, coupling faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of Korea Multimedia Society
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• v.24 no.8
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• pp.1012-1019
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• 2021

Currently, since the black-white QR (Quick Response) codes have limited storage capacity, color QR codes have been actively being studied. By multiplexing 3 colors, the color QR codes can allow the code capacity to be increased by three times, however, the color multiplexing brings about the possibility of crosstalk and noises in the acquisition process of the final image, incurring the decrease of bit-recognition rate. In order to improve the bit recognition rate, while keeping the storage capacity high, this paper proposes a new type of color QR code which uses the pattern information as well as the color information, and then analyzes how to increase the bit recognition rate. For this aim, the paper presents an efficient system which extracts embedded information from color QR code and then, through practical experiments, it is shown that the proposed color QR codes improves the bit recognition rate and are useful for commercial applications, compared to the conventional color codes.

• 보존과학연구
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• s.26
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• pp.41-56
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• 2005

A set of horse bit from the Eonnam-ri site consists of three parts, pyo , ham , andinsu , and each part takes a shape of a piece of bar. According to current typological study, the pyo is S type, the insu is two-braided line type, and the outer rim of the ham is double rim type, respectively. According to X-ray test, inlaid design seems to have been decorated on the whole surface of the iron bit, originally. However, inlaid pattern partially remained. While the part of bit stopper is designed with flame pattern, the part of rein joint is designed with cloud pattern. According to XRF and XGT analysis of inlaid material, the content of silver is not more than 50%. The line inlay method making grooves on the surface of iron, then in laying a silver thread into them, and grinding the surface in a direction was adoptedin the manufacture of the iron bit.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.15 no.2
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• pp.121-125
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• 2015

In this paper, we propose a method that extracts features from character patterns using the fractal dimension of chaos theory. The input character pattern image is converted into time-series data. Then, using the modified Henon system suggested in this paper, it determines the last features of the character pattern image after calculating the box-counting dimension, natural measure, information bit, and information (fractal) dimension. Finally, character pattern recognition is performed by statistically finding each information bit that shows the minimum difference compared with a normalized character pattern database.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.346-349
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• 2011

In this paper, we design a perceptually invisible dot pattern layout and its recognition scheme, and we apply the recognition scheme into a smart self learning aid for interactive learning aid. To increase maximum information capacity and also increase robustness to the noises, we design a ECC (error correcting code) based dot pattern with directional vector indicator. To make a smart self-learning aid, we embed the micro dot pattern (20 information bit + 15 ECC bits + 9 layout information bit) using K ink (CMYK) and extract the dot pattern using IR (infrared) LED and IR filter based camera, which is embedded in the smart pen. The reason we use K ink is that K ink is a carbon based ink in nature, and carbon is easily recognized with IR even without light. After acquiring IR camera images for the dot patterns, we perform layout adjustment using the 9 layout information bit, and extract 20 information bits from 35 data bits which is composed of 20 information bits and 15 ECC bits. To embed and extract information bits, we use topology based dot pattern recognition scheme which is robust to geometric distortion which is very usual in camera based recognition scheme. Topology based pattern recognition traces next information bit symbols using topological distance measurement from the pivot information bit. We implemented and experimented with sample patterns, and it shows that we can achieve almost 99% recognition for our embedding patterns.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.5
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• pp.285-293
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• 2013

The procedure of the arbitration which is the tag collision is essential because the multiple tags response simultaneously in the same frequency to the request of the Reader. This procedure is known as Anti-collision and it is a key technology in the RFID system. In this paper, we propose the Bit Pattern Prediction Algorithm(BPPA) for the efficient identification of the multiple tags. The BPPA is based on the tree algorithm using the time slot and identify the tag quickly and efficiently using accurate bit pattern prediction method. Through mathematical performance analysis, We proved that the BPPA is an O(n) algorithm by analyzing the worst-case time complexity and the BPPA's performance is improved compared to existing algorithms. Through MATLAB simulation experiments, we verified that the BPPA require the average 1.2 times query per one tag identification and the BPPA ensure stable performance regardless of the number of the tags.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.703-706
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• 2003

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.

• Journal of the Korea Society for Simulation
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• v.14 no.1
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• ETRI Journal
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• v.26 no.6
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Convergence Security Journal
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• v.14 no.5
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• pp.17-24
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• 2014

This study proposed LDP (Local Directional Pattern) as a new local micro pattern for facial expression recognition to solve noise sensitive problem of LBP (Local Binary Pattern). The proposed method extracts 8-directional components using $m{\times}m$ mask to solve LBP's problem and choose biggest k components, each chosen component marked with 1 as a bit, otherwise 0. Finally, generates a pattern code with bit sequence as 8-directional components. The result shows better performance of rotation and noise adaptation. Also, a new local facial feature can be developed to present both PFF (permanent Facial Feature) and TFF (Transient Facial Feature) based on the proposed method.