• Journal of the Korean Orthopaedic Association
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• v.56 no.6
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• pp.535-539
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• 2021

Vascular complications following a femoral fracture are rare but can result in serious issues. Several case studies have reported pseudoaneurysms occurring after direct trauma or the insertion of a proximal femoral nail in the case of a proximal femoral fracture. The authors encountered an 85-year-old patient treated with retrograde intramedullary nail fixation for a distal femur fracture and suffered a decrease in the hemoglobin level, swelling, and pain on the 9^th day after surgery. The authors initially attributed the temporary hematoma and pain to ordinary postoperative processes. On the 16^th day after surgery, a pseudoaneurysm originating from the descending branch of the lateral femoral convolutional artery was diagnosed and treated by percutaneous vascular embolization. After the procedure, the hemoglobin level increased, and the swelling and pain decreased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.15-23
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• 2009

Microprocessors, which need correct arithmetic operations, have been the subject of in-depth research in relation to soft errors. Of the existing microprocessor devices, the memory cell is the most vulnerable to soft errors. Moreover, when soft errors emerge in a memory cell, the processes and operations are greatly affected because the memory cell contains important information and instructions about the entire process or operation. Users do not realize that if soft errors go undetected, arithmetic operations and processes will have unexpected outcomes. In the field of architectural design, the tool that is commonly used to detect and correct soft errors is the error check and correction code. The Itanium, IBM PowerPC G5 microprocessors contain Hamming and Rasio codes in their level-2 cache. This research, however, focuses on huge server devices and does not consider power consumption. As the operating and threshold voltage is currently shrinking with the emergence of high-density and low-power embedded microprocessors, there is an urgent need to develop ECC (error check correction) circuits. In this study, the in-output data of the level-2 cache were analyzed using SimpleScalar-ARM, and a 32-bit H-matrix for the level-2 cache of an embedded microprocessor is proposed. From the point of view of power consumption, the proposed H-matrix can be implemented using a schematic editor of Cadence. Therefore, it is comparable to the modified Hamming code, which uses H-spice. The MiBench program and TSMC 0.18 um were used in this study for verification purposes.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.11
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• pp.41-47
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• 2016

High efficiency video coding (HEVC) employs a coding tree unit (CTU) to improve the coding efficiency. A CTU consists of coding units (CU), prediction units (PU), and transform units (TU). All possible block partitions should be performed on each depth level to obtain the best combination of CUs, PUs, and TUs. To reduce the complexity of block partitioning process, this paper proposes the PU mode skip algorithm with region of interest (RoI) selection using motion vector. In addition, this paper presents the CU depth level skip algorithm using the co-located block information in the previously encoded frames. First, the RoI selection algorithm distinguishes between dynamic CTUs and static CTUs and then, asymmetric motion partitioning (AMP) blocks are skipped in the static CTUs. Second, the depth level skip algorithm predicts the most probable target depth level from average depth in one CTU. The experimental results show that the proposed fast CU decision algorithm can reduce the total encoding time up to 44.8% compared to the HEVC test model (HM) 14.0 reference software encoder. Moreover, the proposed algorithm shows only 2.5% Bjontegaard delta bit rate (BDBR) loss.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.61-71
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• 2014

As the occupancy rate of the flash memory increases in the storage media market for the embedded system and the semi-conductor industry grows, the demand and supply of flash memory is increasing by a big margin. They are especially used in large quantity in the smart phones, tablets, PC, SSD and Soc(System on Chip) etc. The flash memory is divided into the NOR type and NAND type according to the cell arrangement structure and the NAND type is divided into the SLC(Single Level Cell) and MLC(Multi Level Cell) according to the number of bits that can be stored in each cell. Many tests have been performed on NOR type such as BIST(Bulit-In Self Test) and BIRA(Bulit-In Redundancy Analysis) etc, but there is little study on the NAND type. For the case of the existing BIST, the test can be proceeded using external equipments like ATE of high price. However, this paper is an attempt for the improvement of credibility and harvest rate of the system by proposing the BIST for the MLC NAND type flash memory of Finite State Machine structure on which the pattern test can be performed without external equipment since the necessary patterns are embedded in the interior and which uses the MLC NAND March(x) algorithm and pattern which had been proposed for the MLC NAND type flash memory.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1566-1573
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• 2016

This paper presents a beam-forming receiver with polyphase In-phase/Quadrature-phase (I/Q) network for airborne communication. In beam-forming receiver, the insertion loss (IL) difference between input path increases the receiver noise figure (NF). The major element for generating IL difference is the impedance variation of phase shifter. In order to maintain a constant IL in every phase, this paper propose a lossless polyphase I/Q network based beam-forming receiver. The proposed lossless polyphase I/Q network has low Q-factor and high impedance for drive back-end VGA (Variable gain amplifier) block with low insertion loss. The 2-stage VGA controls in-phase and quadrature-phase amplitude level for vector summation. The proposed beam-forming receiver prototype is fabricated in TSMC $0.18{\mu}m$ CMOS process. The prototype cover the $360^{\circ}$ with $5.6^{\circ}$ LSB. The average RMS phase error and amplitude error is approximately $1.6^{\circ}$ and 0.3dB.

• Journal of Biomedical Engineering Research
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• v.19 no.6
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• pp.571-575
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• 1998

One of the most significant features of diagnostic ultrasonic instruments is to provide real time information of the soft tissues movements. Echocardiogram has been widely used for diagnosis of heart diseases since it is able to show real time images of heart valves and walls. However, the currently used ultrasonic images are deteriorated due to presence of speckle noises and image dropout. Therefore, it is very important to develop a new technique which can enhance ultrasonic images. In this study, a technique which extracts enhanced binary images in echocardiograms was proposed. For this purpose, a digital moving image file was made from analog echocardiogram, then it was stored as 8-bit gray-level for each frame. For an efficient image processing, the region containing the heat septum and tricuspid valve was selected as the region of interest(ROI). Image enhancement filters and morphology filters were used to reduce speckle noises in the images. The proposed procedure in this paper resulted in binary images with enhanced contour compared to those form the conventional threshold technique and original image processing technique which can be further implemented for the quantitative analysis of the left ventricular wall motion in echocardiogram by easy detection of the heart wall contours.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.9B
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• pp.1742-1754
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• 1999

In this paper, we propose a rate control scheme, using histogram based rate-distortion (R-D) estimation, which produces a consistent picture quality between consecutive frames. The histogram based R-D estimation used in our rate control scheme offers a closed-form mathematical model that enable us to predict the bits and the distortion generated from an encoded frame at a given quantization parameter (QP) and vice versa. The most attractive feature of the R-D estimation is low complexity of computing the R-D data because its major operation is just to obtain a histogram or weighted histogram of DCT coefficients from an input picture. Furthermore, it is accurate enough to be applied to the practical video coding. Therefore, the proposed rate control scheme using this R-D estimation model is appropriate for the applications requiring low delay and low complexity, and controls the output bit-rate ad quality accurately. Our rate control scheme ensures that the video buffer do not underflow and overflow by satisfying the buffer constraint and, additionally, prevents quality difference between consecutive frames from exceeding certain level by adopting the distortion constraint. In addition, a consistent considering the maximum tolerance BER of the voice service. Also in Rician fading channel of K=6 and K=10, considering CLP=$10^{-3}$ as a criterion, it is observed that the performance improment of about 3.5 dB and 1.5 dB is obtained, respectively, in terms of $E_b$/$N_o$ by employing the concatenated FEC code with pilot symbols.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.9 s.351
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• pp.80-87
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• 2006

In this paper, we analyze the performance of IEEE 802.11b WLAN communication between access point(AP) and mobile equipment(ME) in 2.4 GHz band with noise and interference factors. WLAN communication at in-vehicle environment is assumed as the communication between main vehicle controller and electronic device such as sensor, ECU (Electrical Control Unit) in vehicle on telematics field for implementing wireless vehicle control system. Received interference level from other system's mobile equipment in the same band and automobile noise from each part of vehicle can be the main factors that can cause increasing error rate of control signal. With these (actors, we focus on the Eb/No the BER performance of WLAN for analyzing the characteristic of interference factors by the measured bit error rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.

• The Journal of Society for e-Business Studies
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• v.18 no.2
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• pp.153-173
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• 2013

The ontology has been gaining increasing interests by recent arise of the semantic web and related technologies. The focus is mostly on inference query processing that requires high-level techniques for storage and searching ontologies efficiently, and it has been actively studied in the area of semantic-based searching. W3C's recommendation is to use RDFS and OWL for representing ontologies. However memory-based editors, inference engines, and triple storages all store ontology as a simple set of triplets. Naturally the performance is limited, especially when a large-scale ontology needs to be processed. A variety of researches on proposing algorithms for efficient inference query processing has been conducted, and many of them are based on using proven relational database technology. However, none of them had been successful in obtaining the complete set of inference results which reflects the five characteristics of the ontology properties. In this paper, we propose a new index structure called hyper cube index to efficiently process inference queries. Our approach is based on an intuition that an index can speed up the query processing when extensive inferencing is required.