• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.194-197
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• 2003

We proposed Binary ASK system for 1Giga bit Modem. The Binary ASK system has a high speed shutter transmitter and no IF receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs unordinary interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.726-742
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• 2000

A novel rte control algorithm consisting of two major components, i.e. a variable encoding frame rate method and a hybrid DCT/wavelet I-frame coding scheme, is proposed in this work for low bit rate video coding. Most existing rate control algorithms for low bit rate video focus on bit allocation at the macroblock level under a constant frame rate assumption. The proposed rate control algorithm is able to adjust the encoding frame rate at the expense of tolerable time-delay. Furthermore, an R-D optimized hybrid DCT/wavelet scheme is used for effective I-frame coding. The new rate-control algorithm attempts to achieve a good balance between spatial quality and temporal quality to enhance the overall human perceptual quality at low bit rates. It is demonstrated that the rate control algorithm achieves higher coding efficiency at low bit rates with a low additional computational cost. The variable frame rate method and hybrid I-frame coding scheme are compatible with the bi stream structure of H.263+.

• Proceedings of the IEEK Conference
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• summer
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• pp.15-18
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• 2004

In this paper we present a linear discrete bit-loading algorithm that maximizes the transmit bit rate using the channel informations to optimize the performance of the very high-speed digital subscriber line(VDSL) system. It will be useful under the constraint of a maximum transmit power for each user. When the level of crosstalk is high, the power allocation of a user changes the noise experienced by the other users in the same binder. In this case, the performance of DSL modems can be improved by jointly considering the bit and power allocation of all users.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1165-1168
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• 1998

This paper describes a 72-word by 32-bit 2-read/1-write multi-port register file, which is suitable for 32-bit RISC/DSP microprocessors. To minimize area and achieve high speed, advanced single-ended sense amplifiers are used. Each part of circuit is optimized at transistor level. The verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, it was laid out in a 0.6um 1-poly 3-metal layer CMOS technology. The simulation results show maximum operating frequency is 179MHz in worst case conditions. It contains 27,326 transistors and the size is 3.02mm by 2.20mm.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.109-114
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• 2017

In this study, we have developed the active leakage current detection module based on a MSP430 processor, 16bit signal processor. This module can be operated in a desired trip threshold within 0.03 seconds as specified in KS C 4613. This developed module is expected to be applicable as a module for prevention of electric shock in smart distribution panel of smart grid.

• Journal of the Korea Society for Simulation
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• v.14 no.1
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• pp.1-8
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• 2005

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.240-245
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• 2006

Viterbi decoder is composed of BMU(Branch metric Unit), ACSU(Add Compare Select Unit), and SMU(Survivor path Memory Unit). For high speed viterbi decoders, ACSU is the main bottleneck due to the compare-select and feedback operation. Thus, many studies have been advanced to solve the problem. For example, M-step look ahead technique and Minimized method are typical high speed algorithms. In this paper, we designed a bit-level ACSU(K=3, R=1/2, 4bit soft decision) based on those algorithms and switched the matrix product order in the backward direction of Minimized method so as to apply Code-Optimized-Array in order to reduce the area complexity. For experimentation, we synthesized our design by using SYNOPSYS Design compiler, with TSMC 0.18 um library, and verified the timing by using CADENCE verilog-XL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.84-91
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• 2009

A high speed serial link transmitter using multi-level signaling is proposed. To achieve high data rate m high speed serial link, 4-pulse amplitude modulation (PAM) is used. By transmitting 2 bit data in each symbol time, high speed data transmission, two times than binary signaling, is achieved. The transmitter transmits current-mode output instead of voltage-mode output Current-mode output is much faster than voltage-mode output, so higher data transmission is available by increasing switching speed of driver. $2^5-1$ pseudo-random bit sequence (PRBS) generator is contained to perform built-in self test (BIST). The 4-PAM transmitter is designed in Dongbu HiTek $0.18{\mu}m$ CMOS technology and achieves 8 Gb/s, 160 mV of eye height with 1.8 V supply voltage. The transmitter consumes only 98 mW for 8 Gb/s transmission.

• The Journal of the Acoustical Society of Korea
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• v.29 no.3E
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• pp.131-139
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• 2010

This paper proposes a novel spectral hole substitution technique for low bit-rate audio coding. The spectral holes frequently occurring in relatively weak energy bands due to zero bit quantization result in severe quality degradation, especially for harmonic signals such as speech vowels. The enhanced aacPlus (EAAC) audio codec artificially adjusts the minimum signal-to-mask ratio (SMR) to reduce the number of spectral holes, but it still produces noisy sound. The proposed method selectively predicts the spectral shapes of hole bands using either intra-band correlation, i.e. harmonically related coefficients nearby or inter-band correlation, i.e. previous frames. For the bands that have low prediction gain, only the energy term is quantized and spectral shapes are replaced by pseudo random values in the decoding stage. To minimize perceptual distortion caused by spectral mismatching, the criterion of the just noticeable level difference (JNLD) and spectral similarity between original and predicted shapes are adopted for quantizing the energy term. Simulation results show that the proposed method implemented into the EAAC baseline coder significantly improves speech quality at low bit-rates while keeping equivalent quality for mixed and music contents.