• 전자공학회논문지B
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• 제31B권10호
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• pp.67-72
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• 1994

In this paper we suggest a 32 bit high speed parallel multiplier which plays an important role in digital signal processing. We employ a bit-pair recoding Booth algoritham that gurantees n/2 partial product terms, which uniformly handles the signed-operand case. While partial product terms are generated, a special method is suggested to reduce time delay by employing 1's complement instead of 2's complement. Later when partial products are added, the additional 1 bit's are packed in a single partial product term and added to in the parallel counter. Then 16 partial product terms are reduced to two summands by using successive parallel counters. Final multiplication value is obtained by a BLC adder. When this multiplier is simulated under 0.8$\mu$CMOS standard cell we obtain 30ns multiplier speed.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1987년도 한국자동제어학술회의논문집; 한국과학기술대학, 충남; 16-17 Oct. 1987
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• pp.10-13
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• 1987

The main work of this paper are the manufacture of six degree of freedom industrial robot control hardware of 16 bit CPU and the development of five motion control software. The work would draw on KIT of Robotics Laboratory whose extensive experience in these areas; in particular the 68000 assembler and Modula-2 languages, and existing robot control systems. We found that this controller is good for the robot controller of PID types. But, for the use of self-tuning algorithms and real time calculations we need 32 bit CPU robot controller such as MC 68020 microprocessor.

• ETRI Journal
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• 제29권5호
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• pp.691-693
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• 2007

Existing methods to process continuous range queries are not scalable. In particular, as the number of continuous range queries on a large number of moving objects becomes larger, their performance degrades significantly. We propose a novel query indexing method called the projected attribute bit (PAB)-based query index. We project a two-dimensional continuous range query on each axis to get two one-dimensional bit lists. Since the queries are transformed to bit lists and query evaluation is performed by bit operations, the storage cost of indexing and query evaluation time are reduced significantly. Through various experiments, we show that our method outperforms the containment-encoded squares-based indexing method, which is one of the most recently proposed methods.

• 대한임베디드공학회논문지
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• 제4권1호
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• pp.1-8
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• 2009

This paper proposes a 24-bit floating point multiply and accumulate(MAC) unit that can be used in geometry transformation process in 3D graphics. The MAC unit is composed of floating point multiplier and floating point accumulator. When separate multiplier and accumulator are used, matrix calculation, used in the transformation process, can't use continuous accumulation values. In the proposed MAC unit the accumulator can get continuous input from the multiplier and the calculation time is reduced. The MAC unit uses about 4,300 gates and can be operated at 150 MHz frequency.

• 반도체디스플레이기술학회지
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• 제8권1호
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• pp.19-25
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• 2009

Abstract JPEG2000 achieve quality scalability through the rate control method used in the encoding process, which embeds quality layers to the code-stream. This architecture might raise two drawbacks. First, when the coding process finishes, the number and bit-rates of quality layers are fixed, causing a lack of quality scalability to code-stream encoded with a single or few quality layers. Second, in Post compression rate distortion (PCRD) the bit streams after the truncation points discarded. Therefore, computational power for the discarded bit streams is wasted. For solving of problem, through bit rate control, there are many researches. Each proposed algorithms have specially target feature that is improved performance like reducing computational power. Research results have strength and weakness. For the mean time, research contents are reviewed and compared, so we proposed research direction in the future.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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• pp.323-326
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• 2008

This paper describes some field multiplication algorithm over GF($2^m$) on 8-bit processor. Through performance comparisons among algorithm, we show that our proposal is faster than existing algorithms. The proposed algorithm save 26.38% of running time compared with naive comb multiplication algorithm which is a kind of lookup-table (LUT) based algorithm. With the proposed algorithm, a scalar multiplication over GF($2^{163}$) can be computed within 1.04 secs on 8-bit MICAz sensor mote.

• 한국멀티미디어학회논문지
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• 제13권1호
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• pp.102-110
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• 2010

H.264 SVC(Scalable Video Coding)는 디스크 저장 공간 효율성과 높은 확장성을 제공할 수 있는 장점이 있다. 그러나 스트리밍 서버나 단말기는 비트 스트림을 효율적으로 추출해야 한다. 본 논문에서는 네트워크 가용 대역폭을 넘지 않으면서 최대의 PSNR을 얻기 위한 SVC 비트 스트림 추출 기법을 제공한다. 이를 위하여 오프라인시에 최대의 PSNR을 얻기 위한 추출 지점에 대한 정보를 획득한 후, 온라인시에 네트워크 가용 대역폭을 만족하는 비트 스트림의 공간/시간 해상도를 결정한다. 이러한 공간/시간 해상도 정보는 네트워크 가용 대역폭과 함께 비트 스트림 추출기의 입력 파라미터로 사용된다. JSVM 참조 소프트웨어를 활용한 실험을 통하여 본 논문에서 제시한 추출 기법이 높은 PSNR을 제공함을 증명하였다.

• 정보처리학회논문지D
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• 제14D권5호
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• pp.471-482
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• 2007

본 논문에서는 기존 그리드 기반의 질의 색인 기법을 변형하여 보다 적은 저장 공간을 사용하면서 보다 빠른 연산을 수행하는 연속 영역 질의 처리 기법을 제안한다. 제안하는 기법의 주요 특징은 두 가지 이다. 첫째, 각 질의에 비트 식별자를 부여하고 그리드의 각 셀은 이러한 비트 식별자의 조합으로 이루어진 비트 열을 이용하여 질의들의 겹침 정보를 반영한다. 이러한 비트 열을 통해 셀이 어떤 질의들에 포함되어져 있는지 빠르게 판단한 수 있으며, 두 셀 사이의 각 셀을 포함하는 질의 식별자들을 비교하지 않고 비트 열만을 비교하여 질의들의 포함관계를 알아내어 불필요한 연산을 줄일 수 있다. 둘째, 셀들을 그룹단위로 관리하여 불필요하게 비트 열의 길이가 증가하여 저장 공간을 낭비하고 비트 열의 비교 연산 시간이 증가하는 문제를 해결한다. 제안하는 기법이 기존 연속 영역 질의 처리 기법에 비해 우수함을 성능 평가를 통해 입증한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권3호
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• pp.193-197
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• 2013

This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.923-928
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• 1990

This paper describes the design and implementation of a real-time, high-precision vision system and its application to SMT(surface mounting technology) automation. The vision system employs a 32 bit MC68030 as a main processor, and consists of image acquisition unit. DSP56001 DSP based vision processor, and several algorithmically dedicated hardware modules. The image acquisition unit provides 512*480*8 bit image for high-precision vision tasks. The DSP vision processor and hardware modules, such as histogram extractor and feature extractor, are designed for a real-time excution of vision algorithms. Especially, the implementation of multi-processing architecture based on DSP vision processors allows us to employ more sophisticated and flexible vision algorithms for real-time operation. The developed vision system is combined with an Adept Robot system to form a complete SMD system. It has been found that the vision guided SMD assembly system is able to provide a satisfactory performance for SND automation.