• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.109-114
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• 2004

A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.1
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• pp.29-34
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• 2011

In this paper, we propose and analyze the equalizer schemes, zero-forcing (ZF) and minimum mean square error (MMSE) in power line communication (PLC) system for automatic meter reading (AMR). For efficient implementation of AMR system with PLC, effects of impulsive noise and multipath channel should be mitigated. To overcome these effects, the above equalizer schemes are employed. System performance is evaluated in term of bit error rate. From simulation results, it is confirmed that the equalizer can significantly improve bit error rate (BER) performance in PLC system, and MMSE equalizer provides better performance than ZF scheme. The results of this paper can be applied to AMR system as well as various smart grid services using PLC.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.6
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• pp.481-488
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• 2022

This study proposes compensation methods for the initial position error and torque ripple in vector control of two-phase hybrid stepping motors. Stepping motors have an asymmetrical structure due to misalignment, such as the eccentricity generated by the manufacturing and assembly process. When vector control is applied using the position information measured by an incremental encoder attached to the rotor shaft of such stepping motors, the following problems occur. First, an initial position error occurs during the forced excitation process for the initial rotor position alignment. Second, torque ripple corresponding to the mechanical rotation frequency is generated. In this study, these non-ideal phenomena that occur in vector control of the stepping motor are analyzed, and compensation methods are proposed to eliminate them. The validity of the proposed initial position error and torque ripple compensation methods is verified through experiments on a two-phase hybrid stepping motor drive system.

• International Journal of Computer Science & Network Security
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• v.24 no.3
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• pp.182-188
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• 2024

Hardware components are an integral part of Hardware Define Radio (HDR) for seamless operations and optimal performance. On the other hand, Software Define Radio (SDR) is a program that does not rely on any hardware components for its performance. Both of the latter radio programmers utilize modulation functions to make their core components from signal processing viewpoint. The following paper concentrates on SDR based modulation and their performance under different modulations. The bit error rate (BER) of modulations such as PSK, QAM, and PSAM were used as indicators to test channel quality estimation in planar Rayleigh fading. Though it is not commonly used for channel fading, the method of the adder determines the regionally segmented channel fading. Thus, the estimation error of the channel change substantially reduces the performance of the signal, hence, proving to be an effective option. Moreover, this paper also elaborates that BER is calculated as a function of the sample size (signal length) with an average of 20 decibels. Consequently, the size of the results for different modulation schemes has been explored. The analytical results through derivations have been verified through computer simulation. The results focused on parameters of amplitude estimation error for 1dB reduction in the average signal-to-noise ratio, while the combined amplitude deviation estimation error results are obtained for a 3.5 dB reduction

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.2
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• pp.15-21
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• 2007

In this paper, we propose a technique of a practical symbol acquisition and tracking using a low complex ADC and simple digital circuits for noncoherent asynchronous impulse-radio-based Ultra Wideband (IR-UWB) receiver based on energy detection. Compared to previous approaches of detecting an exact acquisition time that require much hardware resource, the proposed technique is to detect the target symbol by finding the symbol acquisition interval per symbol with a target symbo, thus the complexity of the complete signal processing and power consumption by ADC are reduced. To do this, we define the bit decision window (BDW) and analyze the relation between SNR, hardware resource, size of BDW and BER(Bit Error Rate). Using the results, the optimum BDW size for the minimum BER with limited hardware resource is selected. The proposed synchronization technique is verified with an aid of a simulator programmed by considering practical impulse channels.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.715-718
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• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• Journal of electromagnetic engineering and science
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• v.10 no.2
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• pp.50-55
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• 2010

Orthogonal Frequency Division Multiplexing(OFDM) dual-hop systems can take full advantages of the techniques of both multi-hop communication and OFDM. To achievethis end, we propose a joint subcarrier matching, power allocation and bit loading algorithm operating under a total power constraint and the same Bit Error Rate(BER) threshold over all subcarriers. Simulation results demonstrated system throughput improvement compared to single-hop systems and dual-hop systems with different bit loading algorithms for each relay position, power constraint, and required BER.

• Journal of Communications and Networks
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• v.12 no.5
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• pp.475-479
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• 2010

The clipping value, defined as the log-likelihood ratio (LLR) in the case wherein all the list of candidates have the same binary value, is investigated, and an effective method to estimate it is presented for iterative tree search detection. The basic principle behind the method is that the clipping value of a channel bit is equal to the LLR of the maximum probability of correct decision of the bit to the corresponding probability of erroneous decision. In conjunction with multilevel bit mappings, the clipping value can be calculated with the parameters of the number of transmit antennas, $N_t$; number of bits per constellation point, $M_c$; and variance of the channel noise, $\sigma^2$, per real dimension in the Rayleigh fading channel. Analyses and simulations show that the bit error performance of the proposed method is better than that of the conventional fixed-value method.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.1
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• pp.14-22
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• 1998

The Mathematic model of bit synchronization charge-pump Phase Locked Loop (PLL) is presented which takes into account the aperiodic reference pulses and the leakage current of the loop filter. We derive theoreitcal static phase error, overload and stability of bit synchronization charge-pump PLL using presented model and compare it with one of the conventional charge-pump PLL model. We can analysis bit synchronization charge-pump PLL exactly because our model takes into account the leakage current of the loop filter and aperiodic input data which are the charateristics of bit synchronization charge-pump PLL. We also verify it using HSPICE simulation with a bity synchronizer circuit.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1393-1396
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• 2002

무선 ATM(Asynchronous Transfer Mode) 망을 기본으로 하여 ATM망에서 사용하는 서비스 종류인 CBR(Constant Bit Rate), rtVBR(Real-Time Variable Bit Rate), nrtVBR(Non-Real-Time Variable Bit Rate), ABR(Available Bit Rate), UBR(Unspecified Bit Rate)에 따른 플로우를 우선 각 서비스 흐름에 따라서 공평하게 패킷 스케줄링 한다. 그리고 각 서비스 종류에 따라 대역이나 지연에 따라 모든 사용자의 다양한 서비스 트래픽에 공평하게 서비스하는 구조를 갖는다. 아울러 무선 통신망 채널에 에러가 발생할 경우를 고려하여 각 서비스 트래픽에 대한 QoS(Quality of Service)를 보장해주는 무선 ATM 통신망에서 동작하는 스케줄링 알고리즘을 제안하여 시뮬레이션과을 통해 기존의 방법과 성능을 비교하여 기존의 유선 통신망 스케줄링 알고리즘과 달리 무선망의 에러에 대한 각 트래픽의 에러에 대한 성능 향상에 대해 알아본다.