• 한국통신학회논문지
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• 제19권4호
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• pp.679-684
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• 1994

전체 부호화 비트중 일부 비트이 수신만으로도 나은 양호한 영상을 재생할 수 있는 DCT 부화화 영상의 최적 비트 정열에 의한 점진적 전송을 제안하였다. 이는 한 비크 더 전송함으로서 재생 영상의 왜곡을 가장 많이 줄이는 비트부터 단계적으로 전송하는 것이다. 이를 위해서 Embedded 양자화기의 재생 레벨과 한비트 더 전송함으로서 얻어지는 새로운 재생 레벨과 차의 제곱을 의미하는 PTF를 정의하였으며 부호화 비트에대한 PTF를 순차 정렬함으로서 비트 전송 순서를 얻었다. 결과로 제안한 방법은 기존의 zig-zag주사에 의한 전송보다 동일 비트율에서 작은 왜곡과 보다 나은 화질을 갖는 영상을 재생할 수 있었다.

• 한국정보통신학회논문지
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• 제10권3호
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• pp.413-420
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• 2006

본 논문에서는 현재 900MHz 대역의 RRD에서 사용하는 ISO18000-6의 규격 중 Type-B의 전송 프로토콜과 충돌방지 알고리즘을 개선해보고자 FPGA를 이용하여 RFID 시스템을 설계 및 구현하였고 그 성능을 측정하였다 제안한 RFID 시스템에서의 충돌 방지 알고리즘을 기존의 이진 트리 알고리즘 및 bit-by-bit 알고리즘과 성능을 비교 분석하였다. 태그의 개수가 증가할수록 제안한 알고리즘이 기존 알고리즘보다 우수한 성능을 보임을 OPNET 모의실험을 통하여 검증하였다. 개선한 Type-B의 전송 프로토콜과 충돌 방지 알고리즘은 Xilinx사의 FPGA 디자인 툴인 ISE7.1i를 사용하여 설계 하였으며 Xilinx사의 FPGA 디바이스인 Spartan2칩에 구현하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제5권10호
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• pp.1814-1829
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• 2011

In this paper, we present a model-based video bit rate estimation scheme for reducing the bit rate while maintaining a given target quality in many video streaming services limited by network bandwidth, such as IPTV services. Each item of video content can be stored on a video streaming server and delivered with the estimated bit rate using the proposed scheme, which consists of the following two steps: 1) In the first step, the complexity of each intra-frame in a given item of video content is computed as a frame feature to extract a group of candidate frames with a lot of bits. 2) In the second step, the bit rate of the video content is determined by applying statistical analysis and hypothesis testing to that group. The experimental results show that our scheme can reduce the bit rate by up to 78% with negligible degradation of subjective quality, especially with the low-complexity videos commonly used in IPTV services.

• 조명전기설비학회논문지
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• 제29권3호
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.310-318
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• 2016

Emerging technologies such as the Internet of Things (IoT) and the Advanced Driver Assistant System (ADAS) often have image transmission functions with tough constraints, like low power and/or low delay, which require that they adopt line-based, low memory compression methods instead of existing frame-based image compression standards. Bit rate control in the conventional frame-based compression systems requires a lot of hardware resources when the scope of handled data falls at the frame level. On the other hand, attempts to reduce the heavy hardware resource requirement by focusing on line-level processing yield uneven image quality through the frame. In this paper, we propose a bit rate control that maintains consistency in image quality through the frame and improves the legibility of text regions. To find the line characteristics, the proposed bit rate control tests each line for ease of compression and the existence of text. Experiments on the proposed bit rate control show peak signal-to-noise ratios (PSNRs) similar to those of conventional bit rate controls, but with the use of significantly fewer hardware resources.

• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• 전자공학회논문지CI
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• 제47권5호
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• pp.10-16
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• 2010

XML은 점점 데이터 교환과 정보 관리에서 중요하게 여겨진다. 따라서 XML 문서들을 접근, 질의, 저장하는 효율적인 방법들을 개발하기 위한 많은 노력이 진행되고 있다. 본 논문은 XML 문서들을 효율적으로 군집화 하는 새로운 기법을 제안한다. XML 문서를 군집화하기 위해 문서를 대표하는 비트 벡터를 제안한다. 두 XML 문서의 유사도는 대응하는 두 비트 벡터간의 bit-wise AND 연산에 의해서 측정된다. 실험 결과 XML 문서의 특징으로 비트 벡터가 사용되었을 때 군집화가 제대로 그리고 효율적으로 형성됨을 알 수 있다.

• Journal of information and communication convergence engineering
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• 제8권5호
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• pp.539-543
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• 2010

We present a random bit generator that uses fingerprint image for the source of random, and random bit generator using fingerprint image for the randomness has not been presented as yet. Fingerprint image is affected by the operational environments including sensing act, nonuniform contact and inconsistent contact, and these operational environments make FPI to be used for the source of random possible. Our generator produces, on the average, 9,334 bits a fingerprint image in 0.03 second. We have used the NIST SDB14 test suite consisting of sixteen statistical tests for testing the randomness of the bit sequence generated by our generator, and as the result, the bit sequence passes all sixteen statistical tests.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.59-62
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• 2000

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권3호
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.