• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2032-2041
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• 1998

In this work, we propose a novel bit allocation method that is to minimize overall distortions subject ot the bit rate constraint. We partition the original bitallocation problem into 'macroblock level bit allocation' problems that can be solved by conventional Lagrangian mutiplier methods and a 'frame level bit allocation' problem. To tackle the frame level problem, 'two-phase optimization' algorithm is used with iter-frame dependency model. While the existing approaches are almost impossible to find the macroblock-unit result for the moving picture coding system due to high computational complexity, the proposed algorithm can drastically reduce the computational loads by the problem partitioning and can obtain the result close to the optimal solution. Because the optimally allocated results can be used as a benchmark for bit allocation methods, the upper performance limit, or a basis for approximation method development, we expect that the proposed algorithm can be very useful for the bit allocation related works.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.5C
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• pp.498-504
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• 2009

A high-performance low-complexity decoding algorithm for LDPC codes is proposed in this paper, which has the advantages of both bit-flipping (BF) algorithm and sum-product algorithm (SPA). The proposed soft bit-flipping algorithm requires only simple comparison and addition operations for computing the messages between bit and check nodes, and the amount of those operations is also small. By increasing the utilization ratio of the computed messages and by adopting nonuniform quantization, the signal-to-noise ratio (SNR) gap to the SPA is reduced to 0.4dB at the frame error rate of 10-4 with only 5-bit assignment for quantization. LDPC codes with high column or row weights, which are not suitable for the SPA decoding due to the complexity, can be practically implemented without much worsening the error performance.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.161-164
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• 2000

The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.267-270
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• 1999

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. In the case that ROM is used for sinusoidal value calculation, reducing the size of ROM is significant. So the power consumption is affected mostly by its bit width. In the proposed method, the ROM bit width is reduced by 1 bit using the phase subtraction and the approximation. The spurious level is better than 80㏈c and the power consumption estimated is 510㎼/MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2836-2849
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• 1996

Over ATM network, variable bit rate(or VBR) traffic is allowed. Control of VBR traffic is allowed. Control of VBR traffic becomes difficult if it is bursty. VBR video traffic becomes so much bursty during intra frame period that much cell loss would occur when satistical multiplexed in ATM swich. To aviod cellloss, extra communication resources should be allocated, which reduces the capability of an ATM channel. In this paper, we propose two methods which enable a channel limited in resources to serve more VBR MPEG video bit streams. Firstly, we could redue the bitrate fluction of a statiscally multiplexed bundle of VBR video bit streams by reducing the number of intra frames overlapped at the same frame period. This method can be used in ATM switch which controls multiple video sources. Secondary, in two layer enoding, statistical multiplexing gains can be icreased by letting peak bit rate durations of both layers not be overlapped. This results in more smooth traffic. The performance of proposed methods are demonstrated by a proposed calculation method of statistical multiplexing gains(or SMGs.) The proposed SMG is based on both delay and cell loss QoS requirements at the same time.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.113-122
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• 2006

In this paper, we propose a fuzzy method to control bit-rate in the DCT Domain. The method consists of a bit-rate allocation with fuzzy measures and a least-distortion bit-rate reduction. Fuzzy measures are calculated by the code length, the discontinuity ambiguity, and the neighborhood momentum in each DCT block. These measures are summed with weights and form a reduction fuzziness to indicate the degree of preferable reduction. Using the reduction fuzziness. each DCT block is filtered by the least-distortion reduction method to adjust the bit-rate for the target bandwidth. In the experiment, we show the results that the transcoded video quality by the method is better and the bandwidth is more regular than those of existing methods in both visually and quantitatively.

• Journal of Sensor Science and Technology
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• v.20 no.6
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• pp.412-419
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• 2011

In this paper, we used the inter-bit noise detection method in order to reduce the effects of noise light in a visible light identification system that uses a visible LED as a carrier source. A visible light identification system consists of a reader and a transponder. When the enable signal from the reader is detected, the transponder encodes the response data in RZ(Return-to-Zero) bit stream and sends response signal by modulating a visible LED. The reader detects the response signal mixed with noise light, samples the noise voltage in each blank low time between data bits of the RZ signal, and recovers the original data by subtracting the sampled noise from the received signal. In experiments, we improved the signal-to-noise ratio by 20dB using the inter-bit noise detection method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1487-1504
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• 1997

In this paper, the two-stage variable block-size multiresolution motion algorithm is proposed for an interframe coding scheme in the wavelet decomposition. An optimal bit allocagion between motion vectors and the prediction error in sense of minimizing the total bit rate is obtained by the proposed algorithm. The proposed algorithm consists of two stages for motion estimatation and only the first stage can be separated and run on its own. The first stage of the algorithm introduces a new method to give the lower bit rate of the displaced frame difference as well as a smooth motion field. In the second stage of the algorithm, the technique is introduced to have more accurate motion vectors in detailed areas, and to decrease the number of motion vectors in uniform areas. The algorithm aims at minimizin gthe total bit rate which is sum of the motion vectors and the displaced frame difference. The optimal bit allocation between motion vectors and displaced frame difference is accomplished by reducing the number of motion vectors in uniform areas and it is based on a botom-up construction of a quadtree. An entropy criterion aims at the control of merge operation. Simulation resuls show that the algorithm lends itself to the wavelet based image sequence coding and outperforms the conventional scheme by up to the maximum 0.28 bpp.

• Geophysics and Geophysical Exploration
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• v.7 no.1
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• pp.70-79
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• 2004

We have examined the applicability of the triaxial drill-bit VSP method (TAD-VSP) to the geological survey of possible sites for a high-level radioactive waste disposal repository. The seismic energy generated by a drill bit is measured by a downhole multi-component detector, and the resulting signals are processed to image the geological structure deep underground. In order to apply the TAD-VSP method to civil-engineering-scale drilling, we have developed a small but highly sensitive and precise three-component downhole seismic measurement system, and recorded drill-bit signals at a granite quarry. We have successfully imaged discontinuities in the granite, possibly related to fractures, as highly reflective zones. The discontinuities imaged by the TAD-VSP method correlate well with the results of other borehole observations. In conclusion, the TAD-VSP method is usable in geological investigations for civil engineering because the equipment is compact and it is simple to acquire the drill-bit signal.

• ETRI Journal
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• v.38 no.1
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• pp.185-194
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• 2016

In this paper, a novel rate control scheme for low delay video coding of High Efficiency Video Coding (HEVC) is proposed. The proposed scheme is developed by considering a new temporal prediction structure of HEVC. In the proposed scheme, the relationship between bit rate and quantization step is exploited firstly to formulate an accurate quadratic rate-quantization (R-Q) model. Secondly, a method of determining the quantization parameters (QPs) for the first frames within a group of pictures is proposed. Thirdly, an accurate frame-level bit allocation method is proposed for HEVC. Finally, based on the proposed R-Q model and the target bit allocated for the frame, the QPs are predicted for coding tree units by using rate-distortion (R-D) optimization. We compare our scheme against that of three other state-of-the-art rate control schemes. Experimental results show that the proposed rate control scheme can increase the Bjøntegaard delta peak signal-to-noise ratio by 0.65 dB and 0.09 dB on average compared with the JCTVC-I0094 and JCTVC-M0036 schemes, respectively, both of which have been implemented in an HEVC test model encoder; furthermore, the proposed scheme achieves a similar R-D performance to Wang's scheme, as well as obtaining the smallest bit rate mismatch error of all the schemes.