• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.420-423
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• 2015

This paper proposes a method of non-linearity error detection and calibration for binary-weighted charge-driven DACs. In general, the non-linearity errors of DACs often occur due to the mismatch of layout designs or process variation, even when careful layout design methods and process calibration are adopted. Since such errors can substantially degrade the SNDR performance of DAC, it is crucial to accurately measure the errors and calibrate the design mismatches. The proposed method employs 2 identical DAC circuits. The 2 DACs are sweeped, respectively, by using 2 digital input counters with a fixed difference. A comparator identifies any non-linearity errors larger than an acceptable discrepancy. We also propose a calibration method that can fine-tune the DAC's capacitor sizes iteratively until the comparator finds no further errors. Simulations are presented, which show that the proposed method is effective to detect the non-linearity errors and calibrate the capacitor mismatches of a 12-bit DAC design of binary-weighted charge-driven structure.