• ETRI Journal
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• 제26권5호
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• pp.486-492
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• 2004

The emergence of wide channel bandwidth wireless standards requires the use of a highly linear, wideband integrated CMOS baseband chain with moderate power consumption. In this paper, we present the design of highly linear, wideband active RC filters and a digitally programmable variable gain amplifier. To achieve a high unity gain bandwidth product with moderate power consumption, the feed-forward compensation technique is applied for the design of wideband active RC filters. Measured results from a $0.5{\mu}m$ CMOS prototype baseband chain show a cutoff frequency of 10 MHz, a variable gain range of 33 dB, an in-band IIP3 of 13 dBV, and an input referred noise of 114 ${\mu}Vrms$ while dissipating 20 mW from a 3 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.309-317
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• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.168-173
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• 2004

A low power CMOS receiver baseband analog circuit based on alternating filter and gain stage is reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in $0.18\;{\mu}m$ CMOS technology and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.

• 대한전자공학회논문지
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• 제24권1호
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• pp.10-14
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• 1987

Considering transition gating of the input unipolar NRZ signal, the equivalent linear time-invariant model has been derived for the PLL in the timing clock recovery circuits. The magnitude of the alignment and accumulated jitter has been found along a chain of repeaters. For the timing recovery circuit of 90 Mbps optical communication system, the computer simulation shows that, for the first stage of the chain, the alignment jiter and the accumulated jitter are of -5.1766 dB and for the 7-th stage, the alignment jitter and accumulated jitter have the value of -1.0193dB, 4.9053 dB respectively.

• Journal of Communications and Networks
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• 제18권2호
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• pp.162-172
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• 2016

The placement of the complete baseband processing in a centralized pool results in high data rate requirement and inflexibility of the fronthaul network, which challenges the energy and cost effectiveness of the cloud radio access network (C-RAN). Recently, redesign of the C-RAN through functional split in the baseband processing chain has been proposed to overcome these challenges. This paper evaluates, by mathematical and simulation methods, different splits with respect to network level energy and cost efficiency having in the mind the expected quality of service. The proposed mathematical model quantifies the multiplexing gains and the trade-offs between centralization and decentralization concerning the cost of the pool, fronthaul network capacity and resource utilization. The event-based simulation captures the influence of the traffic load dynamics and traffic type variation on designing an efficient fronthaul network. Based on the obtained results, we derive a principle for fronthaul dimensioning based on the traffic profile. This principle allows for efficient radio access network with respect to multiplexing gains while achieving the expected users' quality of service.

• 디지털산업정보학회논문지
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• 제9권2호
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• pp.81-87
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• 2013

In this paper, we present an implementation of Long Term Evolution (LTE) Uplink (UL) system on a Software Defined Radio (SDR) platform using a conventional Personal Computer (PC), which adopts Graphic Processing Units (GPU) and Universal Software Radio Peripheral2 (USRP2) with URSP Hardware Driver (UHD) for SDR software modem and Radio Frequency (RF) transceiver, respectively. We have adopted UHD because UHD provides flexibility in the design of transceiver chain. Also, Cognitive Radio (CR) engine have been implemented by using libraries from UHD. Meanwhile, we have implemented the software modem in our system on GPU which is suitable for parallel computing due to its powerful Arithmetic and Logic Units (ALUs). From our experiment tests, we have measured the total processing time for a single frame of both transmit and receive LTE UL data to find that it takes about 5.00ms and 6.78ms for transmit and receive, respectively. It particularly means that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE UL system.

• 한국통신학회논문지
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• 제36권5A호
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• pp.432-440
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• 2011

4세대 이동통신에서 LTE-Advanced 시스템은 최대 1Gbps의 전송 속도를 구현하기 위해 최대 l00MHz의 넓은 주파수 대역을 필요로 한다. 그러나 현재의 상태에서는 이러한 넓은 대역의 주파수를 얻기가 힘들어 대안으로 여러개의 조각난 대역을 합쳐서 사용하는 Carrier Aggregation기법이 제안되었다. 기본적으로 Carrier Aggregation과 같이 다중 대역을 통해 수신되는 신호는 대역별 여러 개의 수신기를 이용해 각각의 대역별로 병렬 수신 처리하는 Multi-Chain방식이 사용되는데 이는 효과적인 방법이 아니다. 그러므로 본 논문에서는, Time division Multiplexing(TDM)방법을 이용하여 단일 수신기로 수신할 수 있는 방법을 연구한다. TDM 방식은 수신된 여러 대역의 신호를 시간적으로 나누어 수신하고 하나의 DSP를 통해 처리할 수 있는 방식이다. 그런데, 이러한 TDM 방식 기반에서는 Sampling Timing Offset (STO)에 의하여 심각하게 성능 왜곡이 발생하게 된다. 그러므로 본 연구에서는 TDM 방식 기반에서 발생하는 샘플링 타이밍 오프셋의 영향을 분석한다. 그리고 그 분석을 통해 구한 STO 추정 값을 이용하여 보상하는 방법을 제안한다. 마지막으로 시뮬레이션을 통해 BER 성능을 확인하고 제안된 시스템이 OFDM 기반의 시스템에서 다중 대역을 단일 수신기로 수신하는 방법에 적합함을 보인다.