• Transactions on Electrical and Electronic Materials
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• v.14 no.5
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• pp.250-253
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• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.3
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• pp.198-203
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• 2013

Dye-sensitized solar cells (DSSCs) based on titanium dioxide ($TiO_2$) have been extensively studied because of their promising low-cost alternatives to conventional semiconductor based solar cells. DSSCs consist of molecular dye at the interface between a liquid electrolyte and a mesoporous wide-bandgap semiconductor oxide. Most efforts for high conversion efficiencies have focused on dye and liquid electrolytes. However, interface engineering between dye and electrode is also important to reduce recombination and improve efficiency. In this work, for interface engineering, we deposited semiconducting ferroelectric $BiFeO_3$ with bandgap of 2.8 eV on $TiO_2$ nanoparticles and nanotubes. Photovoltaic properties of DSSCs were characterized as a function of thickness of $BiFeO_3$. We showed that ferroelectric $BiFeO_3$-coated $TiO_2$ electrodes enable to increase overall efficiency of DSSCs, which was associated with efficient electron transport due to internal electric field originating from electric polarization. It was suggested that engineering the dye-$TiO_2$ interface using ferroelectric materials as inorganic modifiers can be key parameter for enhanced photovoltaic performance of the cell.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.74-80
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• 2023

Gallium oxide (Ga₂O₃) thin films were grown on c-, a-, m-, r-plane sapphire substrates using a mist chemical vapor deposition system. Various growth temperature range of 400~600℃ was applied for Ga₂O₃ thin film deposition. Then, several structural properties were characterized such as film thickness, crystal phase, lattice orientation, surface roughness, and optical bandgap. Under the certain growth temperature of 500℃, all grown Ga₂O₃ featured rhombohedral crystal structures and well-aligned preferred orientation to sapphire substrate. The films grown on c-and r-plane sapphire substrates, showed low surface roughness and large optical bandgap compared to those on a-and m-plane substrates. Therefore, various sapphire orientation can be potentially applicable for future Ga₂O₃-based electronics applications.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.34-38
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• 2002

기존에 제안된 도파관 스위치의 경우, 도파관의 E-plane에 PBG 기판을 내장하게 되는데, 이 경우 PBG 기판의 저항값을 조절해주는 MEMS 스위치의 바이어스 라인에 대한 문제점이 발생한다 본 논문에서는 PBG 기판을 도파관의 H-plane에 놓음으로써 바이어스 라인을 RF로부터 쉽게 분리하고, 또한 단일 공진 주파수를 갖는 PBG의 경우에 제한된 기판의 길이로 인하여 bandwidth가 좁아지는 문제점을 서로 다른 공진 주파수를 갖는 PBG 기판의 연결을 통해서 bandwidth를 약 80%이상 증가시킬 수 있음을 보였다.

• Proceedings of the KIEE Conference
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• 2005.11a
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• pp.60-61
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• 2005

Electrodes were fabricated on a single ZnO nanowire by photolithography process, metal evaporation, and lift-off. The slow photoresponses of the ZnO nanowire under the continuous illumination of 325nm-wavelength light (corresponding to above-bandgap excitation) indicate that the traps related to oxygen vacancy disturb the flow of electron in ZnO nanowire. The photoresponse and PL spectra were measured, and observed that the excitonic band in the PL spectrum was absent in the photoresponse.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.05a
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• pp.10-10
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• 2004

유전율이 서로 다른 물질을 나노 크기로 주기적으로 배열하여 황자 띠간격(Photonic bandgap)을 이루게 하는 광결정(Photonic crystal)에 인위적인 결함을 부가하여 광파워 분배 및 Mux/Demux 등 광회로 기능 수행을 할 수 있도록 집적화한 광도파로 소자가 미래형 정보통신사회를 위한 초고집적화, 초고속화, 저전력 및 신기능 등의 특성을 위하여 요구된다. 이러한 나노 광결정 소자는 다양한 방법으로 제작이 시도되고 있는데, 나노 임프린트 기술은 실장밀도가 높으며, 수십 나노급의 패턴이 주기적으로 배열된 구조물의 성형에 큰 장점이 있어서 본 연구에서 다루어졌다.(중략)

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.3
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• pp.182-189
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• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.221-224
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• 2012

This paper presents a CMOS interface circuit for MEMS acceleration sensor. It consists of a capacitance to voltage converter(CVC), a second-order switched-capacitor (SC) integrator and comparator. A bandgap reference(BGR) has been designed to supply a stable bias to the circuit and a ${\Sigma}{\Delta}$ Modulator with chopper - stabilization(CHS) has also been designed for more suppression of the low frequency noise and offset. As a result, the output of this ${\Sigma}{\Delta}$ Modulator increases about 10% duty cycle when the input voltage amplitude increases 100mV and the sensitivity is x, y-axis 0.45v/g, z-axis 0.28V/g. This work is designed and implemented in a 0.35um CMOS technology with a supply voltage of 3.3V and a sampling frequency of 3MHz sampling frequency. The size of the designed chip including PADs is $0.96mm{\times}0.85mm$.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.9-14
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• 2008

In this paper, a new type of Yagi-Uda antenna that operates in the terahertz frequencies is designed. The proposed Yagi-Uda antenna can obtain high input resistance of approximately $2000{\Omega}$ at the resonance frequency by using a full-wavelength dipole instead of a half-wavelength dipole as the driver element. The current leakage into the bias line was minimized by applying the photonic bandgap structure to the bias line. By designing the antenna on a thin substrate, the impedance lowering of an antenna caused by the relative dielectric constant of the substrate was prevented and the end-fire radiation pattern which is the original radiation characteristic of the Yagi-Uda antenna could be obtained. We expect that the proposed Yagi-Uda antenna can achieve increased terahertz output power by improving the impedance mismatching problem with the photomixer.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.65-71
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• 1997

We present heterojunction solar cells with a structure of metal/a-Si:H(n-i-p)/poly-Si(n-p)/metal for the terrestrial applications. This cell consists fo two component cells: a top n-i-p junction a-Si:Hi cell with wide-bandgap 1.8eV and a bottom n-p junction poly-Si cell with narrow-bandgap 1.1eV. The efficiency influencing factors of the solar cell were investigated in terms of simulation an experiment. Three main topics of the investigated study were the bottom cell with n-p junction poly-Si, the top a-Si:H cell with n-i-p junction, and the interface layer effects of heterojunction cell. The efficiency of bottom cell was improved with a pretreatment temperature of 900$^{\circ}C$, surface polishing, emitter thickness of 0.43$\mu\textrm{m}$, top Yb metal, and grid finger shading of 7% coverage. The process optimized cell showed a conversion efficiency about 16%. Top cell was grown by suing a photo-CVD system which gave an ion damage free and good p/i-a-Si:H layer interface. The heterojunction interface effect was examined with three different surface states; a chemical passivation, thermal oxide passivation, and Yb metal. the oxide passivated cell exhibited the higher photocurrent generation and better spectral response.