• Journal of electromagnetic engineering and science
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• v.4 no.1
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• pp.37-42
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• 2004

In this paper, LNB(low noise block) downconverter MMIC is designed for Ku-band satellite communication system using InGaP/GaAs HBT high linear process. Designed MMIC consists of low noise amplifier, double balanced mixer, and IF amplifier with a total chip area of 2.6${\times}$1.1 $\textrm{mm}^2$. Designed MMIC has the characteristics of over 37.5 ㏈ conversion gain, 14 ㏈ noise figure, ripple of 3 ㏈, and output-referred $P_{1dB}$TEX>(1 ㏈ compression power) of 2.5 ㏈m with total power dissipation of 3 V, 50 mA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.920-927
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• 1994

A development of an efficient 14.0~14.5GHz 3 Watt SSPA is described in this paper, which is applicable to the very small aperture terminal(VSAT) for bidirectional data and voice signal transmission in low cost and with small size. The SSPA consists of two stages of low noise amplifiers using the low noise GaAs FETs. two stages of medium power amplifiers using the medium power GaAs FETs, and three stages of power amplifiers including a balanced amplifier using an internally matched power GaAs FET. The achieved with this seven stage amplifiers are 42dB signal power gain, 7dB noise figure, 35dBm output power at 1dB gain compression point and 2.0 and 1.5 input and output VSWR respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.11
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• pp.928-931
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• 2017

This paper presents a 2 GHz pulse generator in balanced configuration for ground penetrating radar(GPR). In order to improve the input and output matching, the pulse generator is designed in balanced configuration with $90^{\circ}$ hybrid couplers. The designed pulse generator was fabricated using PCB process. The fabricated pulse generator draws 1 mA current from a 5 V power supply with 27.6 % efficiency. The measured output voltage swing is $3.7V_{pp}$ at 100 MHz pulse repetition frequency(PRF). The pulse width is 2 ns and the input and output return loss is more than 10 dB at the operating frequency of 1.7~2.6 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1079-1086
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• 2012

In this paper, X-band 60 W Solid-State Power Amplifier with sequential control circuit and pulse width variation circuit for improve bias of SSPA module was designed. The sequential control circuit operate in regular sequence drain bias switching of GaAs FET. The distortion and efficiency of output signals due to SSPA nonlinear degradation is increased by making operate in regular sequence the drain bias wider than that of RF input signals pulse width if only input signal using pulsed width variation. The GaAs FETs are used for the 60 W SSPA module which is consists of 3-stage modules, pre-amplifier stage, driver-amplifier stage and main-power amplifier stage. The main power amplifier stage is implemented with the power combiner, as a balanced amplifier structure, to obtain the power greater than 60 W. The designed SSPA modules has 50 dB gain, pulse period 1 msec, pulse width 100 us, 10 % duty cycle and 60 watts output power in the frequency range of 9.2~9.6 GHz and it can be applied to solid-state pulse compression radar using pulse SSPA.

• ETRI Journal
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• v.42 no.4
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• pp.534-548
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• 2020

This study presents a new architecture for a field programmable analog array (FPAA) for use in low-frequency applications, and a generalized circuit realization method for the implementation of nth-order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA-C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA-C symmetric balanced structure for even/odd-nth-order low-pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90-nm complementary metal-oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low-power designs for implementation of biopotential signal processing systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.275-282
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• 1998

In this paper, we designed and fabricated 5-stage microwave solid state power amplifier using balanced amplifier scheme for X-band electronic radar reflector. The used substrate is FR4 and the used active devices are FHX35LC, FLK012WF and FLK022WG. The circuit design and optimization had been carried out through the microwave CAD program CNL2 The measured values show 46dB in gain, input return loss -14.2dB, output return loss -16.6dB and IM3 is 32dBc at designed bandwidth. The measured results are almost agreed with the simulated values.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.11
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• pp.544-547
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• 2006

In this paper, we present a temperature-controlled system for MEMS electrical resistance heaters without a temperature sensor. To rapidly control the heater temperature, the microheater system developed consists of a power supply, power amplifier, digital ${\underline{P}}roportional-{\underline{I}}ntegral-{\underline{D}}ifferential$ (PID) controller, and a quarter bridge circuit with the microheater and three resistors are nominally balanced. The microheaters are calibrated inside a convection oven to obtain the temperature coefficient with a linear or quadratic fit. A voltage amplifier applies the supply voltage proportional to the control signal from the PID controller. Small changes in heater resistance generate a finite voltage across the quarter bridge circuit, which is fed back to the PID controller to compare with the set-point and to generate the control signal. Two MEMS microheaters are used for evaluating the developed control system - a NiCr serpentine microheater for a preconcentrator and a Nickel microheater for ${\underline{P}}olymerase\;{\underline{C}}hain\;{\underline{R}}eaction$ (PCR) chip.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.168-171
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• 2010

본 논문에서는 GaN HEMT 소자를 이용한 고출력 고효율 특성을 가지는 광대역 SSPA의 개발을 다루고 있다. 개발한 SSPA는 8W 급과 15W 급의 GaN HEMT 소자를 사용하여 Pre-Drive 증폭단을 구성하였으며, Drive 증폭단은 50W/150W급 GaN HEMT 소자를 직/병렬구조로 사용하였다. Main 증폭단은 4-way 분배기와 결합기를 이용한 Balanced Structure를 적용하여 높은 출력을 구현하였으며, 안정적인 동작을 위하여 음(-)전원 제어 회로와 출력신호 검출 회로를 포함하고 있다. 제작된 SSPA의 사용가능 대역은 2.9GHz~3.3GHz로 단일전원을 사용하고 있으며 100us 펄스 폭, 10% Duty Cycle 조건에서 60dB의 전압이득, 1kW 출력과 약 28% 효율 특성을 가지는 것으로 측정되었다. 본 논문에서 개발한 SSPA는 S-대역을 사용하는 레이더시스템의 송신단에 적용될 수 있다.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.894-897
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• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.