• Title/Summary/Keyword: BMU 회로

Search Result 2, Processing Time 0.018 seconds

Development of Simulator for Hierarchical Battery Management System (계층적 배터리 관리 시스템 시뮬레이션 기술 개발)

  • Kang, Hyunwoo;Ahn, SungHo;Kim, Dongkyun
    • IEMEK Journal of Embedded Systems and Applications
    • /
    • v.8 no.4
    • /
    • pp.213-218
    • /
    • 2013
  • In this research, we report on the development of simulation system for performance verification of BMS(Battery Management System) which is utilized in electric vehicles. In the industrial circles, a manufacturer of BMS typically tests their system with real battery packs. However, it takes a long time to test all functions of BMS. Here, we develop BMU(Battery Managament Unit) as an embedded board, which will be installed in electric vehicle for controlling battery packs. All other environment factors for testing BMU are developed in softwares in order to reduce the term of test. Especially, the proposed system consists of cell simulator and CMU(Cell Management Unit) simulator which simulate real battery cells and control battery cells. These simulators enable the BMU to test more battery cells. In addition, proposed system provides diagnosis program in order to diagnose and monitor the condition of BMS which makes the test of BMS more easily. In order to verify the performance of the developed simulator, we have performed the experiment with real battery packs and our simulator. Through comparing two results of experiments, we verify that developed simulator shows better performance in terms of less amount of testing duration though having high reliability.

Design of High-performance Viterbi Decoder Circuit by Efficient Management of Path Metric Data (경로 메트릭 데이터의 효율적인 관리를 통한 고성능 비터비 디코더 회로 설계)

  • Kim, Soo-Jin;Cho, Kyeong-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.47 no.7
    • /
    • pp.44-51
    • /
    • 2010
  • This paper proposes the architecture of high-performance Viterbi decoder circuit. The proposed circuit does not require additional memory to calculate the branch metrics because it uses the characteristics of the branch data. The speed of the Viterbi decoder circuit is increased up to 75% by rearranging the path metric data in SRAM and registers properly for fast add-compare-select operations. We described the proposed Viterbi decoder circuit in Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The synthesized circuit consists of 8,858 gates and its maximum operating frequency is 130MHz.