• Korean Journal of Materials Research
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• v.15 no.6
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• pp.413-418
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• 2005

Perovskite $Pb(Ni_{1/3}Nb_{2/3})O_3-Pb(Zr,Ti)O_3[PNN-PZT]$ ceramics were synthesized by conventional ceramic processing technique. In order to modify piezoelectric properties for sensor application in this system, NiO addition was considered to provide $Ni^{+2}$ as an acceptor, which was known to occupy with B site in the structure. The effect of NiO addition up to $8\;mol\%$ on the following piezoelectric properties as well as sintering properties was investigated. When NiO added more than $1\;mol\%$, average grain size was decreased and second phase was found to form. Moreover, the second phase caused decrease in relative dielectric constant $(\varepsilon_{33}T/\varepsilon0)$, electro-mechanical coupling factor $(k_p)$, and piezoelectric charge constant $(d_{33})$, while increasing mechanical quality factor $(Q_m)$. When $1\;mol\%$ NiO was added, density, dielectric properties and piezoelectric properties were abruptly increased.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.596-601
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• 2020

Silicon carbide is considered a potentially useful material for high-temperature electronic devices because of its large band gap energy and p-type or n-type conduction that can be controlled by impurity doping. Accordingly, the thermoelectric properties of -SiC powder prepared by refined diatomite were investigated for high value-added applications of natural diatomite. -SiC powder was synthesized by a carbothermal reduction of the SiO₂ in refined diatomite using carbon black. An acid-treatment process was then performed to eliminate the remaining impurities (Fe, Ca, etc.). n-Type semiconductors were fabricated by sintering the pressed powder at 2000℃ for 1~5h in an N2 atmosphere. The electrical conductivity increased with increasing sintering time, which might be due to an increase in carrier concentration and improvement in grain-to-grain connectivity. The carrier compensation effect caused by the remaining acceptor impurities (Al, etc.) in the obtained -SiC had a deleterious influence on the electrical conductivity. The absolute value of the Seebeck coefficient increased with increasing sintering time, which might be due to a decrease in the stacking fault density accompanied by grain or crystallite growth. On the other hand, the power factor, which reflects the thermoelectric conversion efficiency of the present work, was slightly lower than that of the porous SiC semiconductors fabricated by conventional high-purity -SiC powder, it can be stated that the thermoelectric properties could be improved further by precise control of an acid-treatment process.

• Korean Journal of Materials Research
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• v.23 no.1
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• pp.35-40
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• 2013

In this study, the influence on the surface passivation properties of crystalline silicon according to silicon wafer thickness, and the correlation with a-Si:H/c-Si heterojunction solar cell performances were investigated. The wafers passivated by p(n)-doped a-Si:H layers show poor passivation properties because of the doping elements, such as boron(B) and phosphorous(P), which result in a low minority carrier lifetime (MCLT). A decrease in open circuit voltage ($V_{oc}$) was observed when the wafer thickness was thinned from $170{\mu}m$ to $50{\mu}m$. On the other hand, wafers incorporating intrinsic (i) a-Si:H as a passivation layer showed high quality passivation of a-Si:H/c-Si. The implied $V_{oc}$ of the ITO/p a-Si:H/i a-Si:H/n c-Si wafer/i a-Si:H/n a-Si:H/ITO stacked layers was 0.715 V for $50{\mu}m$ c-Si substrate, and 0.704 V for $170{\mu}m$ c-Si. The $V_{oc}$ in the heterojunction solar cells increased with decreases in the substrate thickness. The high quality passivation property on the c-Si led to an increasing of $V_{oc}$ in the thinner wafer. Short circuit current decreased as the substrate became thinner because of the low optical absorption for long wavelength light. In this paper, we show that high quality passivation of c-Si plays a role in heterojunction solar cells and is important in the development of thinner wafer technology.

• Korean Journal of Materials Research
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• v.7 no.3
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• pp.196-202
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• 1997

Perovskite lanthanum doped lead titanate ($(Pb,La)TiO_{3}$ or PLT) thin films were successfully fabricated on Pt/TijSiO.iSi substrates at the temperatures as low as $440~500^{\circ}C$ by eleclron cyclotron resonance plasma-enhanced chemical vapor deposition (ECR PECVII). Since the volatilities of the MC sources arid oxide molecules (especially Ph oxide) increased with increasing deposition temperature, the film deposition rate and the (I'b + La)/'Ti ratio decreased Stoichiometric perovskite PL'T films with good dielectric and leakeage current properties were obtained at the temperatures of $460~480^{\circ}C$. The lanthanum content of the film was nearly directly propotional to $La(DPM)_{3}$ flow rate. As the La/Ti ratio increased from 3.0 to 9.5%, the dielectric constant increased from 360 to 650 and the leakeage current density at 100kV/cm electric field decreased from $4{\times}10^{-5}$ to $4{\times}10_{-8}A/cm^2$.