• 해양환경안전학회지
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• 제24권7호
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• pp.870-874
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• 2018

선박은 해양사고 발생 시 최악의 경우 퇴선을 해야 하나 특성상 협소하고 복잡하며 해상에서 운항하므로 퇴선이 쉽지 않다. 특히, 여객선의 경우 해상에서의 안전훈련을 이수하지 않은 불특정 다수의 승객들로 인해 더욱 퇴선이 어려운 상황이 된다. 이런 경우 승무원들의 피난 유도가 상당히 중요한 역할을 하게 된다. 그리고 구조자가 사고 선박에 진입하여 구조 활동을 하는 경우 어느 구역으로 진입해야 가장 효과적인지에 대한 검토가 필요하다. 일반적으로 승무원 및 구조자는 최단경로를 택하여 이동하는 것이 일반적이나 최단 경로에 사고 상황 등이 발생했을 경우 제2의 최적 경로 선택이 필요하다. 이러한 상황을 해결하기 위해 이 연구에서는 머신러닝(Machine learning)의 기법 중에 하나인 강화학습(Reinforcement Learning)의 Q-Learning 이용하여 퇴선 경로를 산출하고자 한다. 강화학습은 인공지능(Artificial Intelligence)의 가장 핵심적인 기능으로 현재 여러 분야에 사용되고 있다. 현재까지 개발된 대부분의 피난분석 프로그램은 최단 경로를 탐색하는 기법을 사용하고 있다. 이 연구에서는 최단경로가 아닌 최적경로를 분석하기 위해 머신러닝의 강화학습 기법을 이용하였다. 향후 AI기법인 머신러닝은 자율운항선박의 최적항로 선정 및 위험요소 회피 등 다양한 해양관련 산업에 적용 가능할 것이다.

• 예술인문사회 융합 멀티미디어 논문지
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• 제8권3호
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• pp.945-953
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• 2018

본 논문은 무인수상정의 자율운항을 위한 장애물 탐지 및 회피기동을 위해 3차원 라이다를 사용하였다. 단일센서만을 사용해서 해상조건에서의 무인수상정 장애물 회피운항을 하는데 목적이 있다. 3차원 라이다는 Quanergy사의 M8센서를 사용하여 주변 환경 장애물 데이터를 (r, ��, ��)로 수집하며 장애물 정보에는 Layer 정보와 Intensity 정보를 포함한다. 수집된 데이터를 3차원 직각좌표계로 변환을 하고, 이를 2차원 좌표계로 사상한다. 2차원 좌표계로 변환한 장애물 정보를 포함하는 데이터는 수면위의 잡음데이터를 포함하고 있다. 그래서 기본적으로 무인수상정을 기준으로 가상의 관심영역을 정의하여서 규칙적으로 생성되는 잡음데이터에 대해서 삭제를 하였으며, 그 이후에 발생하는 잡음데이터는 Vector Field Histogram으로 계산된 히스토그램 데이터에서 Threshold를 정해 밀도값에 비례하여 잡음데이터를 제거하였다. 제거된 데이터를 이용하여 무인수상정의 움직임에 따른 상대물체를 탐색하여 가상의 격자지도에 1 Cell씩 저정하면서 데이터의 밀도 지도를 작성하였다. 작성된 장애물 지도를 폴라 히스토그램을 생성하고, 경계값을 이용하여 회피방향을 선정하였다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}