• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.122-131
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• 2000

In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2832-2839
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• 1997

In this paper, a testing architecture and procedure that an idle ATM virtual channel can be utilized for TCP channel is proposed. Four kinds or methodologies for protocol conformance testing have been standardized in ISO. Remote testing method used popularly have some disadvantages that developer must operate system manually in case of System Under Test (SUT) active testing and we cannot control and observe Implementation Under Test (IUT) often. It is proper to adopt distribute testing method than remote test in order to maximize test coverage and optimize fault coverage for conformance testing in ATM systems, and it is required that TCP channel is prepared for distribute testing method. The proposed architecture can adopt distributed testing method without extra physical channel for testing control. Also we can maximize the test coverage and implement the automation of testing without intervention of operator sustaining normal operation of ATM equipment.

• Journal of Korea Multimedia Society
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• v.7 no.5
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• pp.713-720
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• 2004

In this paper we suggest error control scheme to improve CLR performance degradation on wireless ATM access networks which consist of access node and wireless channel. Based on the cell scale and hurst scale, traffic model of wireless ATM access network is analyzed. The CLR equation due to buffer overflow for wireless access node is derived for VBR traffic. the CLR equation due to random bit errors and burst errors for wireless channel is derived. Using the CLR equation for both access node and wireless channel, the CLR equation of wireless ATM access network is derived, and we evaluate the CLR performance on the wireless ATM access networks with conventional SR ARQ scheme and recommended error control scheme, that is, Type I Hybrid ARQ scheme. It is confirmed that CLR performance of the access networks with recommended error control schemes is superior to that of access networks with conventional error control scheme.

• The KIPS Transactions:PartC
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• v.11C no.5
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• pp.645-652
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• 2004

In this paper, we aggregate multi-links information between boundary nodes using the line segment scheme that aggregates topology in-formation within PG referring bandwidth and delay parameter. The proposed scheme can search multi-links efficiently using the depth priority method based on hop count instead of searching all links. To do this, we propose a modified line segment algorithm using two line segment method that represents two points which consist of delay-bandwidth pair to reduce topology information and provide a flexibility to the multi pie-links aggregation. And we apply it to current star topology aggregation. To evaluate performance of the proposed scheme, we compare/analyze the current method with the proposed scheme with respect to call success rate, access time and crankback rate. Through the simulation result analysis, the proposed star topology aggregation scheme presents the better performance than existing scheme.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.80-91
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• 2002

A general goal of the AT%(Asynchronous Transfer Mode) network is to support connect across various network. On ATM networks, ABR services are provided using the remained ban after allocation CBR and VBR traffic. Realtime services such as transmitting audio or video data may be provided using CBR ado VBR which have a constrained transmission delay, but in these cases, the communications bandwidth may be wasted. In this paper a simulation has been performed to compare and evaluate the performance between the ERICA(Explicit Rate Indicate Avoidance) and EPRCA(Enhanced Proportional Rate Control Algorithm) switches which use Explicit Rate switch algorithm for ABR switch. The variation of the ACR at the source end system, the queue length, the utilization rate of the link bandwidth and the share fairness at the transient and steady states are used as the evaluation criteria for the simulation. As a result of simulation, ERICA algorithm switch was ten times long compared to ERPCA switch to achieve assigned fair share. so EPRCA switch is superior to ERICA about load response. For Fair share and stability, ERICA switch is excellent to EPRCA switch.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.119-125
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• 2000

A network of Asynchronous Transfer Mode (ATM) will be required to carry the traffics(CVR, VBR, UBR, ABR) generated by a wide range of services. The algorithm of WRR cell multiplexing is designed to serve no only CBR, VBR traffic but also ABR, UBR traffic in ATM. BSW algorithm was Proposed to carry on manage buffer efficiently at implementing of WRR scheduler. But, BSW a1gorithm cause serious degradation to the weight of each VC and the ratio of scheduler throughput because it allocates more weight than the weight allocated actually in VC and because it could not serve cell if the VC queue is empty. In this paper, we propose the WRR scheduling algorithm of BSW structure which improves the cell service ratio and cell delay. The proposed algorithm is capable of maintaining an allocated VC's weight correctly and decrease of average cell delay by serving other VC cell when empty in each VC queue and increase of cell service ratio as a whole.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.421-429
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• 2000

In present, ATM integrated switching system has been developed to a mixed modules that complexed switching system including maintenance, operation based on B-ISDN/LAN service and plug-in module, , which runs on workstation computer system. Meanwhile, workstation has HMI operation system feature including file system management, time management, graphic processing, TMN agent function. The workstation has communicated with between ATM switching module and clients. This computer system architecture has much burden messages communication among processes or processor. These messages communication consume system resources which are socket, message queue, IO device files, regular files, and so on. Therefore, in this paper we proposed new performance modeling with this system architecture. We will analyze the system bottleneck and improve system performance. In addition, in the future, the system has many additional features should be migrated to workstation system, we need previously to evaluate system bottleneck and redesign it. In performance model, we use queueing network model and the simulation package is used PDQ and C-program.

• Journal of KIISE:Information Networking
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• v.27 no.2
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• pp.206-218
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• 2000

Retransmissions on the DLC layer are essential to ABR service providing the low CLR (cell loss ratio) over the unreliable wireless channel with high bit error rate. In the wireless ATM, the DLC layer below ATM layer performs the retransmission and reordering of the cells to recover the cell loss over the wireless channel and by doing so, the effect of the wireless channel characteristics with high bit error rate can be minimized on the ATM layer which is designed under the assumption of the low bit error rate. We propose, in this paper, the schemes to reflect the changes of the transmission rate over the wireless channel on the ABR rate control. Proposed scheme can control the source rate to the changes of the transmission rate over the wireless channel and reduce the required buffer size in the AP (access point). In the simulation, we assume that the DLC layer can inform the ATM layer of the wireless channel quality as good or bad. Our simulation results show that the proposed schemes require the smaller buffer size compared with the existing scheme, enhanced dynamic max rate control algorithm (EDMRCA). It is also shown that the scheme with the intelligent DLC which adjusts the rate to the wireless channel quality not only provides the low CLR with smaller buffer requirement but also improves the throughput by utilizing the wireless bandwidth more efficiently.

• Journal of KIISE:Information Networking
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• v.28 no.4
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• pp.527-539
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• 2001

The wireless asynchronous transfer mode (ATM) system has the advantage of providing the broadband services with various quality-of-service requirements to the mobile terminal efficiently by utilizing the ATM technology developed for the wired ATM system. The available bit rate (ABR) service among various ATM services utilizes the available bandwidth remaining in the ATM link, which allows the efficient bandwidth usage. During the handoff of the mobile terminal, however, the queue length in the access point (AP) which resides in the boundary of the wired ATM network and the wireless ATM network may increase abruptly. In this paper, we propose a scheme which prevents the buffer-overflow and buffer-underflow in the AP during the handoff of the wireless ABR connection in the wireless ATM system using binary feedback rate-based ABR traffic control. This scheme controls the source's cell generation rate during both handoff period and some time interval after the completion of the handoff procedure. The simulation results show that the proposed scheme prevents the buffer-overflow and buffer-underflow. The proposed scheme can contribute to increasing the throughput of the wireless ABR service during handoff by preventing the buffer overflow and underflow during handoff period.