• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.711-714
• /
• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.715-718
• /
• 2005

Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.321-324
• /
• 2002

Nowadays variable delay arithmetic units have been used for implementing a datapath of\ulcorner target system in pursuit of performance improvement. However. adoption of variable delay arithmetic units requires modification of a typical synchronous control units design methodology. There is a representative approach, which is called a monolithic approach. Although its results are good, its proposed methodology may cause critical problems in the aspects of area and performance with the size increase of initial system specifications. In order to solve this problems, a distributed approach is suggested. Experimental results show that the Proposed method can guarantee original performance of an initial system specification with minimized additional area increase.

• Proceedings of the KIEE Conference
• /
• 2000.11d
• /
• pp.778-780
• /
• 2000

The 74181 is arithmetic logic units(ALU)/function generator. This circuit performs 16 binary arithmetic operations on two 4-bit words. And a full carry look-ahead scheme is made available in this device. The 74181 can also be utilized as a comparator. This circuit has been also designed to provide 16 possible functions of two Boolean variables without the use of external circuitry. This paper analyzes the function of the logic and the implementation adopted in the design of 74181. The understanding of the logic characteristics of this chip enables us to improve future applications.

• Journal of Educational Research in Mathematics
• /
• v.12 no.1
• /
• pp.29-48
• /
• 2002

The purpose of this paper is to investigate the transfer in mathematics learning, especially focussing on arithmetic and algebra. There are many obstacles at the stage of transfer in learning. In the case of mathematics, each learning contents are definitely categorized by the learning level, therefore these obstacles are more happened than other subjects. First of all, this paper investigates the historical transfer from arithmetic to algebra by Sfard's perspectives. And we define prealgebra as the stage between arithmetic and algebra, which may be revised obstacles or misconceptions happened in the early algebra learning. Also, this paper discusses various obstacles and concrete examples happened in the transfer from arithmetic to algebra. To advance the understanding in the learning of algebra, we consider the core contents of the algebra learning which should be stressed at the prealgebra stage. Finally we present the teaching units of (pre)algebra which are sequenced from the variable concepts to equations.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.20-25
• /
• 2009

We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.

• Communications of the Korean Institute of Information Scientists and Engineers
• /
• v.3 no.2
• /
• pp.18-23
• /
• 1985

This paper develops a new theory of multi-valued switching functions and presents simplification method of the multi-valued combinational circuits for realizing N-valued arithmetic units. Multi-valued adders based on the theory proposed here is presented. Switching funtions to composite 10-valued arithmetic units with BCD input are described which is taken into account of using together with 2-valued logic systems.

• Proceedings of the KIEE Conference
• /
• 2001.11c
• /
• pp.153-156
• /
• 2001

This paper analyzes the 74LS381 ALU and designs its equivalent circuit. The 74LS381 ALU is arithmetic logic units(ALUs)/function generators that perform eight binary arithmetic/logic operations on two 4-bit words. However there are only little information to understand and design this circuit. Thus, we not only analyzed it but also designed an equivalent circuit to the 74LS381.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.5
• /
• pp.857-864
• /
• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.837-840
• /
• 2005

This paper presents 3D graphics lighting processor based on vector processing using pipeline chaining. The lighting process of 3D graphics rendering contains many arithmetic operations and its complexity is very high. For high throughput, proposed processor uses pipelined functional units. To implement fully pipelined architecture, we have to use many functional units. Hence, the number of functional units is restricted. However, with the restricted number of pipelined functional units, the utilization of the units is reduced and a resource reservation problem is caused. To resolve these problems, the proposed architecture uses vector processing using pipeline chaining. Due to its pipeline chaining based architecture, it can perform 4.09M vertices per 1 second with 100MHz frequency. The proposed 3D graphics lighting processor is compatible with OpenGL ES API and the design is implemented and verified on FPGA.