• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.335-338
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• 1997

Platinum-Cobalt alloy thin films were deposited on A1$_2$O$_3$substrate by magnetron cosputtering for RTD temperature sensors with wide temperature ranges. We made Pt-Co alloy resistance patterns on the A1$_2$O$_3$substrate by lift-off method and fabricated Pt-Co alley RTD temperature sensors by using Pt-wire, Pt-paste. We investigated the physical and electrical characteristics of theme films under various conditions, input power, working vacuum, annealing temperature and time, and also after annealing these films. The resistivity and sheet resistivity of these films were decreased with increasing the annealing temperature. At input power of Pt : 4.4 W/cm$^2$, Co : 6.91 W/cm$^2$, working vacuum of 10 mTorr and annealing conditions of 800$^{\circ}C$ and 60 min, the resistivity and sheet resistivity of Pt-Co thin films was 15${\mu}$$\Omega$$.$cm and 0.5$\Omega$/ , respectively, and the TCR value of Pt-Co alloy thin films with thickness of 3000${\AA}$ was 3740ppm/$^{\circ}C$ in the temperature range of 25∼600$^{\circ}C$. These results indicate that Pt-Co alloy thin films hove potentiality for the RTD with wide temperature ranges.

• Transactions on Electrical and Electronic Materials
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• v.15 no.5
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• pp.253-256
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• 2014

$Pb(Zr_{0.52}Ti_{0.48})O_3$ thin films of $1.5{\mu}m$ thickness were grown on $Pt/Ti/Gd_3Ga_5O_{12}$ substrate by RF magnetron sputtering at annealing temperatures ranging from $550^{\circ}C$ to $700^{\circ}C$. We evaluated the residual stress, by using a William-Hall plot, as a function of the annealing temperatures of PZT thin film with a constant thickness. As a result, the residual stresses of PZT thin film of $1.5{\mu}m$ thickness were changed by varying the annealing temperature. Also, we measured the hysteresis characteristic of PZT thin films of $1.5{\mu}m$ thickness to evaluate for application of an optoelectronic device.

• Journal of Powder Materials
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• v.15 no.1
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• pp.18-22
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• 2008

The electromagnetic (EM) wave absorption properties with a variation of crystallization annealing temperature have been investigated in a sheet-type absorber using the $Fe_{73}Si_{16}B_7Nb_3Cu_1$ alloy powder. With increasing the annealing temperature the complex permeability (${\mu}_r$), permittivity (${\varepsilon}_r$) and power absorption changed. The EM wave absorber shows the maximum permeability and permittivity after the annealing at $610^{\circ}C$ for 1 hour, and its calculated power absorption is above 80% of input power in the frequency range over 1.5 GHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.107-108
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• 2007

In order to investigate the electrical properties of Hf-silicate as a function of annealing temperature, Hf-silicate deposited by atomic layer deposition (ALD) was studied. After Hf-silicate film deposition, annealing was proceeded at $500^{\circ}C\;and\;700^{\circ}C$. The hysteresis of C-V curves and trapping charge densities were decreased after annealing process. As annealing temperature became higher from $500^{\circ}C\;to\;700^{\circ}C$, the capacitance equivalent thickness (CET) was increased from 1.66 nm to 1.76 nm and the leakage current at -1 V was decreased from $1.70{\times}10^{-4}\;to\;5.68{\times}10^{-5}\;A/cm^2$.

• Journal of the Korean institute of surface engineering
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• v.27 no.4
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• pp.234-240
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• 1994

A large area impurity doping method for poly-Si TFT LCD has been developed. The advantage of this method is the doping of impurities into Si over a large area without mass separation and beam scanning. Phosphorus diluted in hydrogen was discharged by RF(13.56MHz) power and ions from discharged gas were accelerated by DC acceleration voltage and were implanted into deposited Si films. The annealing characteristic of this method was similar to that of the ion implantation method in the low doping concentration. Three mechanisms were evolved in the annealing characteristics of phosphorus doped Si films. Point defects annihilation and the retrogradation of dopant atoms at grain boundaries as a result of grain growth played a major role at low and high annealing temperature, respectively. However, due to the dopant segregation, the reverse annealing range existed at intermediate annealing temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.11
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• pp.859-863
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• 2010

Evolution of surface morphology of ${\alpha}-Al_2O_3$ substrate was investigated as a function of annealing temperature and time. Commercial (0001) ${\alpha}-Al_2O_3$ single crystal substrates were annealed in the range of $600-1000^{\circ}C$ in air. At $600^{\circ}C$, step-terrace structure started to be formed on the substrate. However, the surface roughness on the terrace was still considerable and a number of islands were observed on the step edges as well as the terraces. As the annealing temperature increased, the islands were absorbed into the step edges. Thus the terraces were smoother and the step edges were more straightened. Well-defined surface with a step height of 0.2 nm was formed above $900^{\circ}C$. On the other hand, when the substrate was annealed at a fixed temperature of $1000^{\circ}C$, the change of surface morphology was observed for the substrate annealed for 10 min. After the annealing for 30 min, the surface on which any islands could not survive was observed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.1014-1017
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• 2001

In recent years, The tantalum nitride(TaN) thin-film has been developed for the electronic resistor and capacitor. In this papers, The effect of thermal annealing in the temperature range of 300∼700$^{\circ}C$ on the sheet resistor properties and microistructure of tantalum nitride(TaN) thin-film deposited by RF sputtering was studied. XRD(X-ray diffractometer) and AFM were used to observe electrical properties and microstructrue of the TaN film and sheet resistance. The TCR properties of the TaN films were discussed in terms of annealing temperature, ratio of nitrogen, crystallization and thin films surface morphology due to annealing temperature. The leakage current of the TaN thin film annealed 400 $^{\circ}C$ was stabilized in the study. How its was found that the sheet resistance in the polycrystalline TaN thin film decreased with increasing the annealing temperature above 600 $^{\circ}C$ after sudden peak upen 400 $^{\circ}C$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• Journal of Korean Vacuum Science & Technology
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• v.6 no.2
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• pp.79-83
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• 2002

As Ag does not form my silicide on Si surfaces, Ag wire is a candidate for self-assembled nanowire on the reconstructed and single-domain Si(5 5 12)-2 $\times$ 1. In the present study, various Ag coverages and post-annealing temperatures had been tested to fabricate a Ag nanowire with high aspect ratio. When Ag coverage was less than 0.03 ML and the post-annealing temperature was 500(C, Ag atoms preferentially adsorbed on the tetramer sites resulting in Ag wires with an inter-row spacing of ~5 nm. However, its aspect ratio is relatively small and its height is also not even. On the other hand, the Ag-posited surface completely loses its reconstruction even with the same annealing at 500 $\^{C}$ if the initial coverage exceeds 0.05 ML. But the additional subsequent annealing at 700$\^{C}$ and slow-cooling process recovers the well-ordered Ag chain with relatively high aspect ratio on the same tetramer sites. It can be understood that, in the double step annealing process, the lower temperature annealing is required for cohesion of adsorbed Ag atoms and the higher temperature annealing is for providing Ag atoms to the tetramer sites.