• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.93-96
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• 2000

This paper has been proposed an audio DAC structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter on-a-chip. The passband ripple(< 0.41${\times}$fs), passband attenuation(at 0.41${\times}$fs) and stopband attenuation(> 0.59${\times}$fs) of the Δ$\Sigma$ modulator output using the proposed digital interpolation filter had ${\pm}$ 0.001 ［㏈］, -0.0025［㏈］ and -75［㏈］, respectively. Also the inband group delay was 30.07/fs［s］ and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20［㏈］ approximately at 65［㎑］, out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• 정보학연구
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• 제9권1호
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• pp.33-39
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• 2006

This study is for the contents of development to the hardware system and software driving algorithm to implement the frequency band of about 7KHz los pass digital filter which has the cut-off frequency of 392Hz by interfacing of a microprocessor with its peripheral analog-to-digital converter chip and digital-to-analog converter chip. The simplicity of digital filter design without difficulty and the implementation of programmed digital filter can be realized by providing the interfacing method to implement the law pass digital filter for the biological signals and the realization method of computer algorithm by a microprocessor.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.660-664
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• 2004

The indirect rotor position detection method using terminal voltage of brushless DC motor (BLDCM) requires simple control circuit, and has wide speed range of sensorless operation. However, because the substantial phase difference exists between real back emf and terminal voltage, the existing indirect detection method using analog filter which is affected by frequency, speed, and load sensitively cannot be synchronized with current, in the end, it advances or delays. This paper presents new analog filter circuit design for rotor position estimation in order to solve the problem, and proposes novel sensorless operation method which is stable even in high speed range and not influenced by parameters with analysis on phase difference by load and speed. Moreover, the appropriateness of the proposed sensorless drive in this paper is verified and analyzed by experimentation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 제36회 하계학술대회 논문집 D
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• pp.2513-2515
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• 2005

Recently genetic algorithm techniques have widely used in adaptive and control schemes for production systems. However, generally it costs a lot of time for leaming in the case applied in control system. Furthermore, the physical meaning of genetic algorithm constructed as a result is not obvious. And this method has been used as a learning algorithm to estimate the parameter of a genetic algorithm used for identification of the process dynamics of Butter-Worth analog filter and it was shown that this method offered superior capability over the genetic algorithm. A genetic algorithm is used to solve the parameter identification problem for linear and nonlinear digital filters. This paper goal estimate Butter-Worth analog filter parameter using the genetic algorithm.

• 전자공학회논문지A
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• 제33A권6호
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• pp.32-41
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• 1996

We propose the improved GMSK (gaussian-filtered minimum shift keying) quadrature modulator using the FIR(finite impulse response )filter whose coefficients are obtained form the differnce of phase response, and design its ASIC (applicaton specific integrated circuit) which can be used for GSM (global system for mobile communication) digital cellular system and DCS 1800 (digital cellular system at 1800MHz) personal communication system. Input data become quantized I and Q channel 10 bit signal through cosine and sine ROM mapping after being filtered by the FIR filter whose normalized bandwidth is 0.3 and designed by considering intersymbol interference as well as sampling ratio. These two signals become the GMSK modulated I and Q channel signal through DAC (digital-to-analog converter) and 7th order analog chebyshev LPF(low pass filter) respectively. The difference between the ideal analog signal and its digitized signal is analyzed in terms of sampling noise, quantization noise, truncation noise and coefficient noise. And the effect of the LPF following the DAC is considered. The ASIC design of the GMSK quadrature modulator is also confirmed by an experiment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.309-317
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• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• 한국통신학회논문지
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• 제11권5호
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• pp.315-322
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• 1986

本 論文은 　圓函數를 利用한 IIR digital 필터 設計에 關하여 硏究한 것이다. Digital 　圓函數는 analog 　圓函數로부터 Bilinear z 變換에 依하여 求하였다. Bilinear z 變換된 函數로 digital필터를 設計하면 aliasing 現象은 避할 수 있으나 周波數歪曲이 發生한다. Analog函數를 digital函數로 變換하면 이러한 影響으로 遮斷周波數 領域이 不一致하므로 이것을 避하기 爲하여 prewarping法을 利用하였다. 마지막으로, 컴퓨터 simulation에 依하여 analog 크기 特性과 digital 크기 特性을 比較한 結果, prewarping을 한 digital 크기特性이 analog 크기 特性에 比하여 改善되었음을 確認할 수 있었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• 대한전자공학회논문지SD
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• 제43권11호
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• pp.77-82
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• 2006

직접 변환 방식의 IEEE 802.11a 무선랜 수신기에 사용되는 아날로그 채널 선택 필터에 대하여 기술한다. 채널 선택필터는 10MHz의 차단주파수를 갖는 5차의 체비셰프 필터이며 active-RC 구조로 설계되었다. 2단의 연산증폭기를 사용하였는데, 전력 소모를 최소화하기 위하여 전류재사용 feedforward 주파수 보상 방법을 사용하였다. 필터는 $0.l8{\mu}m$ CMOS 공정을 사용하여 제작하였으며 1.8V의 전원 전압에서 20mW의 전력 소모를 갖고 있으며 19dBV의 out-of-band iIP3를 갖는다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.78-81
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• 2002

We propose a current-mode analog programmable finite-impulse-response (FIR) filter with variable tap circuits. From the circuit simulation, the operation of the 7- tap FIR filter is confirmed. We design and fabricate the 0.0625-step tap circuit using 0.8$\mu\textrm{m}$ CMOS technology. The proposed FIR filter has a variable length of taps and variable coefficients, so it has a potential for being used to software defined radio (SDR) terminals.