• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.77-81
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• 2021

In this paper, a low-csst ECG system using a digital filter was implemented. After amplifying the analog ECG signal, it is converted into a digital signal and filtered. The developed ECG module is miniaturized by removing the analog filter element that occupies the existing volume and replacing it with a digital filter using a 3-stage Butterworth filter which is one of IIR filters. It uses a serial monitoring program with C# to check and save the ECG waveform measured on a computer screen. The ECG system using a developed digital filter in this paper uses a low-cost processor instead of an expensive, high-end processor, and its size and price are reduced by converting the analog filter to a digital filter. In addition, since the waveform of the developed ECG system is similar to the actual ECG waveform of MIT-BIU, it is considered that the existing analog filter can be replaced with the developed digital filter.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.255-259
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• 2008

In this paper, a current-mode integrator for low-voltage, low-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS parameter is performed and achieved 44.9dB gain, 15.7MHz unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12MHz cutoff frequency which is suitable for WCDMA baseband block.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1753-1758
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• 2012

This paper introduces analog FIR filters based on a distributed amplifier and analyzes the proposed filter's characteristics. A simple design method of an analog FIR filter based on the digital filter design technique is also introduced. The proposed analog FIR filters are a moving average(MA) and a comb type filters with no multiplier. This simple structures of the proposed filters may enable to operate at multi-GHz frequency range and applicable to combine a filter and an amplifier of RF system. The proposed analog FIR filters were implemented with standard $0.18{\mu}m$ CMOS technology. The designed GHz analog FIR filters are simulated by Cadence Spectre and compared to the results of digital FIR filters obtained from MATLAB simulations. From the simulation results, the characteristics of the proposed analog FIR filters are fairly well matched with those of digital FIR filters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.1
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• pp.1-9
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• 1994

In general, when IIR digital filter are designed from analog filters, the bilinera transformation and the impluse invariant tramsformation are commonly used. It is known, however, that high frequency response of digital filters designed by these transformations can not be well approximated to the sampled analog signals. In this paper, the symbol pulse invariant transformation is analyzed theoretically so that the symbol pulse invariant transformation which was originally application to a rectangular pulse is newly applied to double rate pulse signals and generic shape pulse signals. Also, the relation of spectra between a transfer function of digital filter and one of analog filter is considered. Further, we apply to design the digital high pass filters using the symbol pulse invariant transformation method.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.52 no.4
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• pp.148-153
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• 2003

In this paper, the low voltage 3V Sigma-Delta Digital Analog Converter(DAC) is designed for using in the transmitter of ADSL analog front-end. We have developed the CMOS DAC according to ANSI T1.413-2(DMT) standard specifications of the chip. The designed 4th-order DAC is composed of three block which are 1-bit DAC, 1st-order Switched-Capacitor filter and analog active 2nd-order Resistor-Capacitor(RC) filter. The HSPICE simulation of the designed DAC showing 65db SNR, is connected with 1.1MHz continuous lowpass filter. And also, we have performed the circuits verification and layout verification(ERC, DRC, LVS) followed by fabrication using TSMC 2-poly 5-metal p-substrate CMOS $0.35{\mu}m$ processing parameter. Finally, the chip testing has been performed and presented in the results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.11
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• pp.1700-1705
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• 2012

This study is focusing on ripple elimination in the band pass filter. There are generally two design methods in IIR filter design, which are a direct method and an indirect one. The indirect design method that designs the digital IIR LPF using the prototype analog LPF is applied to this study. A Butterworth filter and a Chebyshev filter are the typical prototype analog LPFs. This study shows characteristics of the digital IIR LPFs that are transformed from the prototype analog LPFs. The designed Butterworth and Chebyshev IIR LPFs are also designed as the band pass filters by frequency transformation in order to compare with the proposed cascading Chebyshev BPFs. This study shows frequency characteristics between the transformed IIR BPFs and the proposed cascading Chebyshev BPFs as well. The proposed cascading Chebyshev BPF is designed by cascading the different orders of Chebyshev BPFs. The aspect of the cascading filter is offsetting the ripples to descend them while the pass band ripples of the Chebyshev filter are ascending and vice versa. The designed cascading Chebyshev filter shows the flatness and the sharpness, which represent the advantages of Butterworth filter in the pass band and of Chebyshev filter in the transition band respectively. This result verifies the validity of the designed filter.

• ETRI Journal
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• v.32 no.6
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• pp.911-920
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• 2010

This paper presents a method of designing hybrid analog/asymmetrical square-root (SR) FIR filters. In addition to the conventional frequency domain constraints, the proposed method considers time-domain constraints as well, including the inter-symbol interference (ISI) and the opening of the eye pattern at the receiver output. This paper also reviews a systematic way to find the discrete-time equivalence of analog parts in a band-limited digital communication system. Thus, a phase equalizer can be easily realized to compensate for the nonlinear phase responses of the analog components. With the hybrid analog/SR FIR filter co-design, examples show that using the proposed method can result in a more robust ISI performance in the presence of the receiver clock jitter.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.3
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• pp.260-264
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• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1990.10a
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• pp.62-66
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• 1990