• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.7-12
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• 2018

The effects of Ru deposition temperature and post-annealing conditions on the interfacial adhesion energies of atomic layer deposited (ALD) Ru diffusion barrier layer and Cu thin films for the advanced Cu interconnects applications were systematically investigated. The initial interfacial adhesion energies were 8.55, 9.37, $8.96J/m^2$ for the sample deposited at 225, 270, and $310^{\circ}C$, respectively, which are closely related to the similar microstructures and resistivities of Ru films for ALD Ru deposition temperature variations. And the interfacial adhesion energies showed the relatively stable high values over $7.59J/m^2$ until 250h during post-annealing at $200^{\circ}C$, while dramatically decreased to $1.40J/m^2$ after 500 h. The X-ray photoelectron spectroscopy Cu 2p peak separation analysis showed that there exists good correlation between the interfacial adhesion energy and the interfacial CuO formation. Therefore, ALD Ru seems to be a promising diffusion barrier candidate with reliable interfacial reliability for advanced Cu interconnects.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.