• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.18-29
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• 2008

NAND Flash memory has been growing popular storage device for the last years because of its low power consumption, fast access speed, shock resistance and light weight properties. However, it has the distinct characteristics such as erase-before-write architecture, asymmetric read/write/erase speed, and the limitation on the number of erasure per block. Due to these limitations, various Flash Translation Layers (FTLs) have been proposed to effectively use NAND flash memory. The systems that adopted the conventional FTL may result in severe performance degradation by the hot data which are frequently requested data for overwrite in the same logical address. In this paper, we propose a novel FTL algorithm called Adaptive Flash Translation Layer (AFTL) which uses sector mapping method for hot data and log-based block mapping method for cold data. Our system removes the redundant write operations and the erase operations by the separating hot data from cold data. Moreover, the read performance is enhanced according to sector translation that tends to use a few read operations. A series of experiments was organized to inspect the performance of the proposed method, and they show very impressive results.

• The Journal of the Korea Contents Association
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• v.6 no.12
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• pp.40-49
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• 2006

As a promising integrated circuit, wireless communication and micro-computing technology, the technology of sensor network that will lead the information technology industries of the next generation and realize the ubiquitous computing is one of the most active research topics and its research activities are also making today. From now on, each node, the network formation, and even the sensor network itself will interact with the generic network and evolve dynamically according to environmental changes in a process of continual creation and extinction. Therefore, address-internetworking between sensor network and generic network which are used different address mechanism is required. In this paper, we propose a static address-internetworking scheme for interactive networking between a sensor network and the Internet. The proposed scheme that possess a gateway approach to perform the protocol translation from one protocol to another, an overlay approach to constructs an overlay network on the WSNs and enables static internetworking between a sensor network address scheme based on Zigbee and the Internet address scheme based on the Internet Protocol. In addition, we verify the proposed scheme by an interconnection experiment.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.3
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• pp.29-38
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• 1998

This ppaer suggests a congestion control scheme for CL(ConnectionLess) overlay network using the feedback loops getween CL werver, between CL servers, and the header translation table of CL server. The CL overlay network for CBDS(Connectionless Broadband Data Service) defined by ITU0T(International Telecommunication Union-Telecommunication) consists of CL servers which route frames and links which connect between CL user and CL server or between CL servers. In this CL overlay network, two kinds of congestions, link congestion and CL server congestion, may occur. We suggest a scheme that can solve the congestion using ABR(Available Bit Rate) feedback control loop, the traffic control mechanism. This scheme is the link-by-link method suing the ABR feedback control loops between CL user and CL server or between CL servers, and the header translation table of CL server. As CL servers are always endpoints of ABR connections, the congestion staturs of the CL server can be informed to the traffic sources using RM(Resource Management) cell of the ABR feedback loops. Also CL server knows the trafffic sources making congestion by inspecting the source address field of CLNAP-PDUs(ConnectionLess Network Access Protocol - Protocol Data Units). Therefore this scheme can be implemeted easily using only both ABR feedback control loop of ATM layer and the congestion state table using the header translation table of CL server because it does not require separate feedback links for congestion control of CL servers.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.811-813
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• 2004

IPv6는 IPv4 기반의 인터넷의 주소고갈과 새로운 부가 기능 등의 필요성 때문에 IETF에서 IPv4를 대체하기 위해 채택 된 프로토콜이다. 하지만 IPv4를 어느 한순간에 IPv6로 대체하는 것은 불가능하기 때문에 기존 IPv4와의 호환 및 연동을 위한 여러 메커니즘이 연구되었다. 그 중 NAT-PT(Network Address Translation-Protocol Translation)는 IPv4/IPv6 헤더 변환기술을 적용한 대표적인 변환 메커니즘이며, IP 패킷을 통과하는 망의 IP버전에 맞게 변환 시켜서 전송하는 방식이다. 그러나 모든 패킷들이 하나의 NAT-PT 노드로 집중되므로 병목현상이 발생하며, 이로 인해 성능저하가 발생한다. 본 논문은 NAT-PT 병목현상을 줄이기 위한 방안으로 DNS-ALG 기반된 서버를 이용하여 다중 NAT-PT를 사용한 방법을 제안한다.

• Proceedings of the Korean Information Science Society Conference
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• 2001.10c
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• pp.535-537
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• 2001

IPv6 초기 도입단계에서는 IPv4와 IPv6 (Internet protocol version 6)의 혼용이 예상됨에 따라 초기 IPv6 네트워크는 기존 IPv4와의 연동 및 호환을 위해 트랜지션 (transition) 메커니즘과 상호공존 (coexistence mechanism) 메커니즘을 필요로 한다. 이를 위해 다양한 트랜지션 메커니즘들이 제안되고 있는데 크게 터널링 (tunneling)과 변환 (translation) 방식으로 구분할 수 있다. 본 논문은 이러한 메커니즘 중에서 터널링을 이용한 DSTM (dual stack transition mechanism)을 분석한 후 제안된 DSTM의 각 연결별 임시 IPv4 주소할당에 대한 비합리적인 문제점을 개선한 모델을 제시하였다. 본 논문예서 제안한 모델은 기존의 NAT (network address translation) 방식과 유사하게 단일 IPv4 주소와 포트 넘버를 이용하여 각 연결을 식별할 수 있도록 한다. 그리고 DSTM 시스템 구현을 위한 효율적인 알고리즘 설계를 통해 IPv4 패킷을 IPv6 패킷으로 캡슐화 (encapsulation)하여 전송할 수 있는 인터페이스를 구현하여 결과를 분석하였다.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.371-378
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• 2004

This paper presents the implementation and performance of the HVIA-GE card, which is a hardware implementation of the Virtual Interface Architecture (VIA) based on Gigabit Ethernet. The HVIA-GE card is a 32-bit/33MHz PCI adapter containing an FPGA for the VIA protocol engine and a Gigabit Ethernet chip set to construct a high performance physical network. HVIA-GE performs virtual-to-physical address translation, Doorbell, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the HVIA-GE card, and the VIA protocol engine efficiently controls the address translation process by directly accessing the ATT. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show the maximum bandwidth of 93.7MB/s and the minimum latency of 11.9${\mu}\textrm{s}$. In terms of minimum latency HVIA-GE performs 4.8 times and 9.9 times faster than M-VIA and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of HVIA-GE is 50.4% and 65% higher than M-VIA and TCP/IP respectively.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.791-802
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• 1996

In this paper, we discuss a distributed shared memory management scheme based on multi-threaded programming model for a large-scale loosely coupled multiprocessor system. The scheme covers three major issues in the distribued shared memory;the address translation table management, the block coherence maintenance, and the block placement policy. The scheme efficiently resolves the general problems occurred in the distributed shared memory such as a false sharing, an unnecessary replication, a block bouncing, and an address aliasing phenomenon. It also provides the application transparency, good scalability, easy implementation, and multithreaded programming model to users.

• Proceedings of the KAIS Fall Conference
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• 2004.11a
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• pp.225-229
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• 2004

현재 인터넷에서 사용하고 있는 네트워크 계층 프로토콜은 IP 버전 4 인데, 이러한 주소 부족 문제를 해결하고자 IP 주소 필드의 길이가 대폭 확장되는 IPv6 라는 새로운 인터넷 프로토콜을 개발하게 된다(5). 그러나 이러한 신 표준안을 인터넷에 실제로 적용하고 운영하기에는 많은 어려운 문제들이 남아있어 그 대안으로 NAT(Network Address Translation)[1]가 등장하게 된다. 그러나 이러한 NAT 기능은 외부 망으로부터의 접촉이 불가능하다는 특성을 가지고 있다. 이러한 특성은 보안 유지측면에서는 장점으로 작용하나, 소규모 기업이나 사무실이 웹(Web) 서버(Server) 나 메일(mail) 서버등을 두고 싶어하는 경우에는 외부에서의 접근이 허용되어야 하므로 단점이 된다. 본 연구에서는 이러한 단점을 파악하기 위하여 NAT 테이블(table) 에 수정을 가함으로써 사설망내부의 특정 서버에 접근할 수 있는 확장된 개념의 NAT를 제안하고자 한다. 아울러 이러한 NAT 기능을 이용하여 구성된 사설망 간의 연결기능을 제공할 수 있는 방법을 제안함으로써 기존의 가상 사설망(VPN : Virtual Private Network) 외 일부 기능도 수용할 수 있도록 하였다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2903-2913
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• 1997

This paper describes the design and implementation of the ParaC language that supports parallel programming on the shared memory and distributed memory parallel machine. The ParaC language is designed for the effective use of system resources of scalable parallel systems. The goal is achieved by adding parallel and synchronization constructs for shared address spaces, and remote task constructs for distributed address spaces. This paper also shows the translation method, and we implement the translator and the run-time library for parallel execution of extended constructs.