• Title/Summary/Keyword: Adaptive update algorithm

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Efficient Calculation for Decision Feedback Algorithms Based on Zero-Error Probability Criterion (영확률 성능기준에 근거한 결정궤환 알고리듬의 효율적인 계산)

  • Kim, Namyong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.2
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    • pp.247-252
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    • 2015
  • Adaptive algorithms based on the criterion of zero-error probability (ZEP) have robustness to impulsive noise and their decision feedback (DF) versions are known to compensate effectively for severe multipath channel distortions. However the ZEP-DF algorithm computes several summation operations at each iteration time for each filter section and this plays an obstacle role in practical implementation. In this paper, the ZEP-DF with recursive gradient estimation (RGE) method is proposed and shown to reduce the computational burden of O(N) to a constant which is independent of the sample size N. Also the weight update of the initial state and the steady state is a continuous process without bringing about any propagation of gradient estimation error in DF structure.

Time Constant Estimation of Induction Motor rotor using MRAS Fuzzy Control (MRAS 퍼지제어를 이용한 유도전동기 회전자의 시정수 추정)

  • Lee Jung-Chul;Lee Hong-Gyun;Chung Dong-Hwa;Cha Young-Doo
    • The Transactions of the Korean Institute of Power Electronics
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    • v.10 no.2
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    • pp.155-161
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    • 2005
  • This paper presents time a constant estimation of induction motor using MRAS(model reference adaptive system) fuzzy control. The rotor time constant is enabled from the estimation of rotor flux, which has two methods. One is to estimate it based on the stator current and the other is to integrate motor terminal voltage. If the parameters are correct, these two methods must yield the same results. But, for the case where the rotor time constant is over or under estimated, the two rotor nut estimation have different angles. Furthermore their angular positions are related to the polarity of rotor time constant estimation error. Based on these observation, this paper develops a rotor time constant update algorithm using fuzzy control. This paper shows the theoretical analysis as well as the simulation results to verify the effectiveness of the new method.

Polymorphic Path Transferring for Secure Flow Delivery

  • Zhang, Rongbo;Li, Xin;Zhan, Yan
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.8
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    • pp.2805-2826
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    • 2021
  • In most cases, the routing policy of networks shows a preference for a static one-to-one mapping of communication pairs to routing paths, which offers adversaries a great advantage to conduct thorough reconnaissance and organize an effective attack in a stress-free manner. With the evolution of network intelligence, some flexible and adaptive routing policies have already proposed to intensify the network defender to turn the situation. Routing mutation is an effective strategy that can invalidate the unvarying nature of routing information that attackers have collected from exploiting the static configuration of the network. However, three constraints execute press on routing mutation deployment in practical: insufficient route mutation space, expensive control costs, and incompatibility. To enhance the availability of route mutation, we propose an OpenFlow-based route mutation technique called Polymorphic Path Transferring (PPT), which adopts a physical and virtual path segment mixed construction technique to enlarge the routing path space for elevating the security of communication. Based on the Markov Decision Process, with considering flows distribution in the network, the PPT adopts an evolution routing path scheduling algorithm with a segment path update strategy, which relieves the press on the overhead of control and incompatibility. Our analysis demonstrates that PPT can secure data delivery in the worst network environment while countering sophisticated attacks in an evasion-free manner (e.g., advanced persistent threat). Case study and experiment results show its effectiveness in proactively defending against targeted attacks and its advantage compared with previous route mutation methods.

An Adaptive Proximity Route Selection Method in DHT-Based Peer-to-Peer Systems (DHT 기반 피어-투-피어 시스템을 위한 적응적 근접경로 선택기법)

  • Song Ji-Young;Han Sae-Young;Park Sung-Yong
    • The KIPS Transactions:PartA
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    • v.13A no.1 s.98
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    • pp.11-18
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    • 2006
  • In the Internet of various networks, it is difficult to reduce real routing time by just minimizing their hop count. We propose an adaptive proximity route selection method in DHT-based peer-to-peer systems, in which nodes select the nぉe with smallest lookup latency among their routing table entries as a next routing node. Using Q-Routing algorithm and exponential recency-weighted average, each node estimates the total latency and establishes a lookup table. Moreover, without additional overhead, nodes exchange their lookup tables to update their routing tables. Several simulations measuring the lookup latencies and hop-to-hop latency show that our method outperforms the original Chord method as well as CFS' server selection method.

A 200-MHz@2.5V 0.25-$\mu\textrm{m}$ CMOS Pipelined Adaptive Decision-Feedback Equalizer (200-MHz@2.5-V 0.25-$\mu\textrm{m}$ CMOS 파이프라인 적응 결정귀환 등화기)

  • 안병규;이종남;신경욱
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2000.05a
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    • pp.465-469
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    • 2000
  • This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

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A Design of Pipelined Adaptive Decision-Feedback Equalized using Delayed LMS and Redundant Binary Complex Filter Structure (Delayed LMS와 Redundant Binary 복소수 필터구조를 이용한 파이프라인 적응 결정귀환 등화기 설계)

  • An, Byung-Gyu;Lee, Jong-Nam;Shin, Kyung-Wook
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.12
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    • pp.60-69
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    • 2000
  • This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

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A Performance Comparison of CM-MMA and RMMA Blind Equalization Algorithm in QAM Signal Transmission (QAM 신호 전송에서 CM-MMA와 RMMA 블라인드 등화 알고리즘의 성능 비교)

  • Lim, Seung-Gag
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.2
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    • pp.79-84
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    • 2019
  • This paper compare the performance of CM-MMA (Constellation Matching-MMA) and RMMA (Region-based MMA) blind equalization algorithm for improve the QoS by minimizing the intersymbol interference that is occurred in nonlinear communication channel when transmitting the QAM signal. In the tap coefficient update for adaptive, CM-MMA use the error of nonconstant modulus signal adding the current MMA cost fuction and constellation matching error terms of sinusoidal power function, and the RMMA use the error by transfoms the nonconstant modulus signal of equalizer output constellation to 4-QAM constant modulus signal. They has different equalization performance by these error signal, it were compared in this paper by simulation, and performance index such as output signal constellation of equalizer, residual isi, maximum distortion, SER curves are applied for this. As a result of computer simulation, the RMMA has more better performance in the every performance index, convergence speed, residual value, noise robustness compared to CM-MMA.

Self-Adaptive Performance Improvement of Novel SDD Equalization Using Sigmoid Estimate and Threshold Decision-Weighted Error (시그모이드 추정과 임계 판정 가중 오차를 사용한 새로운 SDD 등화의 자기적응 성능 개선)

  • Oh, Kil Nam
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.8
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    • pp.17-22
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    • 2016
  • For the self-adaptive equalization of higher-order QAM systems, this paper proposes a new soft decision-directed (SDD) algorithm that opens the eye patterns quickly as well as significantly reducing the error level in the steady-state when it is applied to the initial equalization stage with completely closed eye patterns. The proposed method for M-QAM application minimized the computational complexity of the existing SDD by the symbol estimated based on the two symbols closest to the observation, and greatly simplified the soft decision independently of the QAM order. Furthermore, in the symbol estimating it increased the reliability of the estimates by applying the superior properties of the sigmoid function and avoiding the erroneous estimation of the threshold function. In addition, the initialization performance was improved when an error is generated to update the equalizer, weighting the symbol decision by the threshold function to the error, resulting in an extension of the range of error fluctuations. As a result, the proposed method improves remarkably the computational complexity and the properties of initialization and convergence of the traditional SDD. Through simulations for 64-QAM and 256-QAM under multipath channel conditions with additive noise, the usefulness of the proposed methods was confirmed by comparing the performance of the proposed 2-SDD and two forms of weighted 2-SDD with CMA.

Efficient VLSI Architecture for Disparity Calculation based on Geodesic Support-weight (Geodesic Support-weight 기반 깊이정보 추출 알고리즘의 효율적인 VLSI 구조)

  • Ryu, Donghoon;Park, Taegeun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.9
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    • pp.45-53
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    • 2015
  • Adaptive support-weight based algorithm can produce better disparity map compared to generic area-based algorithms and also can be implemented as a realtime system. In this paper, we propose a realtime system based on geodesic support-weight which performs better segmentation of objects in the window. The data scheduling is analyzed for efficient hardware design and better performance and the parallel architecture for weight update which takes the longest delay is proposed. The exponential function is efficiently designed using a simple step function by careful error analysis. The proposed architecture is designed with verilogHDL and synthesized using Donbu Hitek 0.18um standard cell library. The proposed system shows 2.22% of error rate and can run up to 260Mhz (25fps) operation frequency with 182K gates.

A Vehicle Detection Algorithm for a Lane Change (차선 변경을 위한 차량 탐색 알고리즘)

  • Ji, Eui-Kyung;Han, Min-Hong
    • Journal of the Institute of Convergence Signal Processing
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    • v.8 no.2
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    • pp.98-105
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    • 2007
  • In this paper, we propose the method and system which determines the condition for safe and unsafe lane changing. To determine the condition, first, the system sets up the Region of Interest(ROI) on the neighboring lane. Second, a dangerous vehicle is extracted during the line changing. Third, the condition is determined to wm or not by calculating the moving direction, relative distance md relative velocity. To set up the ROI, the only one side lane is detected and the interested region is expanded. Using the coordinate transformation method, the accuracy of the ROI raised. To correctly extract the vehicle on the neighboring lane, the Adaptive Background Update method and Image Segmentation method which uses the feature of the travelling road are used. The object which is extracted by the dangerous vehicle is calculated the relative distance, the relative velocity and the moving average. And then in order to ring, the direction of the vehicle and the condition for safe and unsafe is determined. As minimizes the interested region and uses the feature of the travelling road, the computational quantity is reduced and the accuracy is raised and a stable result on a travelling road images which demands a high speed calculation is showed.

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