• Title/Summary/Keyword: ATmega8

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Analysis of Output Characteristics and Frequency Variation Design for Personal High Frequency Electrical Stimulation Medical Devices (개인용 고주파 전기자극기의 주파수 가변 설계 및 출력 특성의 분석)

  • Jang, Kyeong-Wook;Leem, Ji-Hyun;Baek, Seung-Myoung;Shon, Jin-Geun
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.65 no.1
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    • pp.25-30
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    • 2016
  • In this paper, personal electrical stimulation medcial devices using bioelectrical stimulating was developed. Therapy effect of RET(resistive electric transfer) was more effective than CET(capacitive electric transfer), but CET was adopted because of safety issue. Then, the optimum parameters that may be effective in thin skin or facial wrinkles was set. For example, the frequency of the pulse voltage for stimulation is 1.8[MHz], burst frequency is 7[kHz] or 400[Hz], the development of devices was to have ON/OFF control and frequency control. When burst frequency was adjusted 7[kHz], heat was generated in the electrode. The case of 400[Hz] the heat was little generated. The microcontroller ATmega128-based experimental results show that the proposed personal high frequency electrical stimulation devices can be applied to medical equipment using therapy effect successfully.

w-Bit Shifting Non-Adjacent Form Conversion

  • Hwang, Doo-Hee;Choi, Yoon-Ho
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.7
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    • pp.3455-3474
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    • 2018
  • As a unique form of signed-digit representation, non-adjacent form (NAF) minimizes Hamming weight by removing a stream of non-zero bits from the binary representation of positive integer. Thanks to this strong point, NAF has been used in various applications such as cryptography, packet filtering and so on. In this paper, to improve the NAF conversion speed of the $NAF_w$ algorithm, we propose a new NAF conversion algorithm, called w-bit Shifting Non-Adjacent Form($SNAF_w$), where w is width of scanning window. By skipping some unnecessary bit comparisons, the proposed algorithm improves the NAF conversion speed of the $NAF_w$ algorithm. To verify the excellence of the $SNAF_w$ algorithm, the $NAF_w$ algorithm and the $SNAF_w$ algorithm are implemented in the 8-bit microprocessor ATmega128. By measuring CPU cycle counter for the NAF conversion under various input patterns, we show that the $SNAF_2$ algorithm not only increases the NAF conversion speed by 24% on average but also reduces deviation in the NAF conversion time for each input pattern by 36%, compared to the $NAF_2$ algorithm. In addition, we show that $SNAF_w$ algorithm is always faster than $NAF_w$ algorithm, regardless of the size of w.

An Efficient DPA Countermeasure for the $Eta_T$ Pairing Algorithm over GF($2^n$) Based on Random Value Addition

  • Seo, Seog-Chung;Han, Dong-Guk;Hong, Seok-Hie
    • ETRI Journal
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    • v.33 no.5
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    • pp.780-790
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    • 2011
  • This paper presents an efficient differential power analysis (DPA) countermeasure for the $Eta_T$ pairing algorithm over GF($2^n$). The proposed algorithm is based on a random value addition (RVA) mechanism. An RVA-based DPA countermeasure for the $Eta_T$ pairing computation over GF($3^n$) was proposed in 2008. This paper examines the security of this RVA-based DPA countermeasure and defines the design principles for making the countermeasure more secure. Finally, the paper proposes an efficient RVA-based DPA countermeasure for the secure computation of the $Eta_T$ pairing over GF($2^n$). The proposed countermeasure not only overcomes the security flaws in the previous RVAbased method but also exhibits the enhanced performance. Actually, on the 8-bit ATmega128L and 16-bit MSP430 processors, the proposed method can achieve almost 39% and 43% of performance improvements, respectively, compared with the best-known countermeasure.

Enhanced Stream Cipher Rabbit Secure Against Power Analysis Attack (전력분석 공격에 안전한 개선된 스트림 암호 Rabbit)

  • Bae, KiSeok;Ahn, MahnKi;Park, YoungHo;Moon, SangJae
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.1
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    • pp.64-72
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    • 2013
  • Recently, stream cipher Rabbit was selected for the final eSTREAM portfolio organized by EU ECRYPT and as one of algorithm in part of ISO/IEC 18033-4 Stream Ciphers on ISO Security Standardization. However, a feasibility of practical power analysis attack to algorithm in experiment was introduced. Therefore, we propose appropriate methods such as random masking and hiding schemes to secure against power analysis attack on stream cipher Rabbit. We implement the proposed method with increment of 24% operating time and 12.3% memory requirements due to maintaining a high-speed performance. We use a 8-bit RISC AVR microprocessor (ATmegal128L chip) to implement our method for practical experiments, and verify that stream cipher Rabbit with our method is secure against power analysis attack.

An Educational MBL Platform Development with Remote Access Functionality (원격 제어 교육용 MBL 플랫폼 개발에 관한 연구)

  • Kim, Si-Kyung;Lee, Hee-Bok;Lee, Hee-Man
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.8 no.6
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    • pp.1388-1393
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    • 2007
  • The Microprocessor Based Laboratory Systems(MBL) with the remote access functional could put basic science experimental facilities together by providing a modem platform that the students can utilize simultaneously to learn basic physics, chemistry and biology, Our educator target platform combines a highly integrated 8-bit embedded Atmega128 processor and real time embedded OS (operating system), allowing plenty of headroom for follow-on basic science projects for students. The proposed MBL-NUTOS (Microprocessor Based Laboratory-NUT/OS) employed in the lab are available with internet base simulation capabilities, on public servers and students personal PCs, enabling the students to study at home and increasing the opportunity of accessing for the science laboratory facility.

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The Design of Multi-channel Asynchronous Communication IC Using FPGA (FPGA를 이용한 다채널 비동기 통신용 IC 설계)

  • Ock, Seung-Kyu;Yang, Oh
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.1
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    • pp.28-37
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    • 2010
  • In this paper, the IC (Integrated Circuit) for multi-channel asynchronous communication was designed by using FPGA and VHDL language. The existing chips for asynchronous communication that has been used commercially are composed of one to two channels. Therefore, when communication system with two channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 asynchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 256 bytes respectively and consequently high speed communication became possible. To detect errors between communications, it was designed with digital filter and check-sum logic and channel MUX logic so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. It was composed and simulated logic of VHDL described by using Cyclone II Series EP2C35F672C8 and QuartusII V8.1 of ALTERA company. In order to show the performance of designed IC, the test was conducted successfully in QuartusII simulation and experiment and the excellency was compared with TL16C550A of TI (Texas Instrument) company and ATmegal28 general-purpose micro controller of ATMEL company that are used widely as chips for asynchronous communication.

Speed Characteristics of The Thin Cross Ultrasonic Motor (Thin Cross 초음파모터의 속도특성)

  • Jeong, Seong-Su;Jun, Ho-Ik;Chong, Hyon-Ho;Park, Min-Ho;Park, Tae-Gone
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2009.04b
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    • pp.51-51
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    • 2009
  • Thin Cross 초음파모터의 구조는 그림 1(a)와 같이 크로스형태의 얇은 스테이터에 윗면과 아랫면에 각각 8개의 압전세라믹이 부착된 형태이다. 압전세라믹의 분극방향은 로터와 접촉하는 스테이터의 중심부인 네 개의 타 점에서 순차적인 타원변위가 생성되도록 결정된다. 유한요소해석프로그램인 ATILA 5.2.4를 사용하여 최적설계된 모델을 제작하였고, 푸쉬풀 게이지, x-y 스테이지, rpm 메타, 토크 게이지를 이용하여 구동시스템을 구성하였다. 그림 1(b)는 마이크로컨트롤러(ATmega)를 이용한 구동 드라이버를 보여준다. 한 주기에서 1/4분주의 순차적인 네 개 의 구형파를 생성하고, 이를 push-pull회로를 통하여 90도의 위상차가 나는 정현파를 생성하여 초음파 모터의 구동 전원으로 사용한다. 피드백 회로인 맨코더와 AD 컨버터는 정속도 운전을 위해서 사용되었다. 제안된 구동드라이버를 이용하여 측정한 결과, 기존의 제품화된 드라이버와 비교하여도 특성의 큰 차이를 보이지 않았으며 피드백 회로를 통하여 부하변화에 따른 속도의 극심한 변화를 비교적 안정화 시킬 수 있었다. 입력전압을 증가시킬수록 속도는 선형적인 증가를 보였고 토크는 이와 반대로 감소하는 특성을 보였다. 피드백 제어회로가 없는 경우에는 프리로드 변화에 따른 극심한 속도 변화를 보였고, 피드백 제어를 하였을 경우에는 0.2~0.4[N]의 범위에서 정속도 운전이 가능함을 확인하였으며, 장시간의 운전에도 온도 및 속도특성이 안정적인 특성을 보였다.

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Design and Implementation of a Scalable Real-Time Sensor Node Platform (확장성 및 실시간성을 고려한 실시간 센서 노드 플랫폼의 설계 및 구현)

  • Jung, Kyung-Hoon;Kim, Byoung-Hoon;Lee, Dong-Geon;Kim, Chang-Soo;Tak, Sung-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.8B
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    • pp.509-520
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    • 2007
  • In this paper, we propose a real-time sensor node platform that guarantees the real-time scheduling of periodic and aperiodic tasks through a multitask-based software decomposition technique. Since existing sensor networking operation systems available in literature are not capable of supporting the real-time scheduling of periodic and aperiodic tasks, the preemption of aperiodic task with high priority can block periodic tasks, and so periodic tasks are likely to miss their deadlines. This paper presents a comprehensive evaluation of how to structure periodic or aperiodic task decomposition in real-time sensor-networking platforms as regard to guaranteeing the deadlines of all the periodic tasks and aiming to providing aperiodic tasks with average good response time. A case study based on real system experiments is conducted to illustrate the application and efficiency of the multitask-based dynamic component execution environment in the sensor node equipped with a low-power 8-bit microcontroller, an IEEE802.15.4 compliant 2.4GHz RF transceiver, and several sensors. It shows that our periodic and aperiodic task decomposition technique yields efficient performance in terms of three significant, objective goals: deadline miss ratio of periodic tasks, average response time of aperiodic tasks, and processor utilization of periodic and aperiodic tasks.

Development of Sensor Network Simulator using Machine Instruction-level Discrete-Event Simulation (기계명령어-레벨의 이산-사건 시뮬레이션을 이용한 센서 네트워크 시뮬레이터 개발)

  • Jung Yong-Doc;Kim Bang-Hyun;Kim Tae-Kyu;Kim Jong-Hyun
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.11a
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    • pp.769-771
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    • 2005
  • 유비쿼터스 컴퓨팅의 기반 설비인 센서 네트워크는 많은 수의 센서 노드들로 구성되며, 각 센서 노드의 하드웨어는 매우 작은 규모이다. 또한 최소한의 전력 소모를 위하여 센서 노드들은 동적으로 재구성되며, 노드들 간의 통신은 무선 네트워크를 통하여 이루어진다. 센서 네트워크는 구축 목적에 따라 네트워크 토폴로지 및 라우팅 방식이 결정되어야 하고, 이와 더불어 센서 노드의 하드웨어와 소프트웨어도 필요에 따라 다양하게 변경되어야 한다. 따라서 센서 네트워즈가 구현되기 전에 시스템 동작과 성능을 예측할 수 있고 소프트웨어 개발 환경도 제공해주는 시뮬레이터가 사용 가능하다면, 시스템 개발 기간을 크게 단축시킬 수 있을 것이다. 기존의 센서 네트워크 시뮬레이터들은 특별한 응용을 위한 특정 기반의 하드웨어와 운영체제에 국한되어 개발되었기 때문에 다양한 센서 네트워크 환경을 지원하기에는 한계가 있으며, 센서 네트워크 설계상의 주요 요소인 전력 소모량 분석이 포함되지 않았다. 따라서 본 연구에서는 특정한 응용이나 운영체제에 제한을 받지 않으면서 다양하게 센서 네트워크 환경을 설계 및 검증할 수 있고 전력 소모량 추정도 가능한 시뮬레이터를 개발하는 것을 목표로 하였다. 본 연구에서 개발한 시뮬레이터는 기계명령어-레일(machine instruction-level)의 이산-사건 시뮬레이션(discrete-event simulation) 기법을 이용함으로써 실제 센서 노드의 프로그램 실행 및 관련 동작들을 세부적으로 예측하는 데 사용될 수 있도록 하였다. 시뮬레이션의 작업부하(Workload)인 명령어 트레이스(instruction trace)로는 ATmega128L 마이크로컨트롤러용으로 크로스 컴파일된 인텔 헥스-레코드 형식(.hex) 또는 S-레코드 형식(.srec)의 파일을 사용한다.들을 해결하고자 프라이버시보호에 새로운 키 생성 방법을 통한 강력한 프로토콜을 제안 한다.하였으나 사료효율은 증진시켰으며, 후자(사양, 사료)와의 상호작용은 나타나지 않았다. 이상의 결과는 거세비육돈에서 1) androgen과 estrogen은 공히 자발적인 사료섭취와 등지방 침적을 억제하고 IGF-I 분비를 증가시키며, 2) 성선스테로이드호르몬의 이 같은 성장에 미치는 효과의 일부는 IGF-I을 통해 매개될 수도 있을을 시사한다. 약 $70 {\~} 90\%$의 phenoxyethanol이 유상에 존재하였다. 또한, 미생물에 대한 항균력도 phenoxyethanol이 수상에 많이 존재할수록 증가하는 경향을 나타내었다. 따라서, 제형 내 oil tomposition을 변화시킴으로써 phenoxyethanol의 사용량을 줄일 수 있을 뿐만 아니라, 피부 투과를 감소시켜 보다 피부 자극이 적은 저자극 방부시스템 개발이 가능하리라 보여 진다. 첨가하여 제조한 curd yoghurt는 저장성과 관능적인 면에서 우수한 상품적 가치가 인정되는 새로운 기능성 신제품의 개발에 기여할 수 있을 것으로 사료되었다. 여자의 경우 0.8이상이 되어서 심혈관계 질환의 위험 범위에 속하는 수준이었다. 삼두근의 두겹 두께는 남녀 각각 $20.2\pm8.58cm,\;22.2\pm4.40mm$으로 남녀간에 유의한 차이는 없었다. 조사대상자의 식습관 상태는 전체 대상자의 $84.4\%$가 대부분이 하루 세끼 식사를 규칙적으로 하고 있었으며 식사속도는 허겁지겁 빨리 섭취하는 경우가 남자는 $31.0\%$, 여자는 $21.4\%$로 나타났고 이들을 제외한 나머지 사람들은 보통 속도 혹은 충분한 시간을 가지고 식사를 하였

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Design of a Real-time Sensor Node Platform for Efficient Management of Periodic and Aperiodic Tasks (주기 및 비주기 태스크의 효율적인 관리를 위한 실시간 센서 노드 플랫폼의 설계)

  • Kim, Byoung-Hoon;Jung, Kyung-Hoon;Tak, Sung-Woo
    • The KIPS Transactions:PartC
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    • v.14C no.4
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    • pp.371-382
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    • 2007
  • In this paper, we propose a real-time sensor node platform that efficiently manages periodic and aperiodic tasks. Since existing sensor node platforms available in literature focus on minimizing the usage of memory and power consumptions, they are not capable of supporting the management of tasks that need their real-time execution and fast average response time. We first analyze how to structure periodic or aperiodic task decomposition in the TinyOS-based sensor node platform as regard to guaranteeing the deadlines of ail the periodic tasks and aiming to providing aperiodic tasks with average good response time. Then we present the application and efficiency of the proposed real-time sensor node platform in the sensor node equipped with a low-power 8-bit microcontroller, an IEEE802.15.4 compliant 2.4GHz RF transceiver, and several sensors. Extensive experiments show that our sensor node platform yields efficient performance in terms of three significant, objective goals: deadline miss ratio of periodic tasks, average response time of aperiodic tasks, and processor utilization of periodic and aperiodic tasks.