• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.1
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• pp.125-131
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• 2009

In this paper, we proposed the remote visual monitoring system on mobile robot platform. The proposed system is composed of ARM9 core PXA255 processor, micro CMOS camera and wireless network and the captured visual image is transmitted via 803.11b/g wireless LAN(WLAN) for remote visual monitoring operations. Robot platform maneuvering command is transmitted via WLAN from host and the $640{\times}480$, $320{\times}240$ pixel fixed visual image is transmitted to host at the rate of $3{\sim}10$ frames per second. Experimental system is implemented on Linux OS base and tested for remote visual monitoring operation and verified the proposed objects.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.357-360
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• 2005

유전자 알고리즘(Genetic Algorithm, GA)은 자연적 진화과정에서 생존 경쟁 측면의 가장 적합한 메커니즘이다. GA를 소프트웨어로 수행하는데 큰 지연시간은 필수적이기 때문에 하드웨어 설계를 이용하여 알고리즘 실행 속도를 증가시키기 위한 많은 연구가 진행되어 왔다. 본 논문에서는 염색체의 임의의 유전인자를 기준으로 입력 받은 염색체에 대하여 GA 연산을 수행하는 유전 연산자를 설계한다. 설계된 디자인을 ARM 코어와 PLD로 구성된 Altera사의 Excalibur칩에 구현하여 동작을 검증하였다.

• Proceedings of the Korean Fiber Society Conference
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• 2002.04a
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• pp.199-202
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• 2002

The synthesis of materials with controlled composition and architectures continues to be a focus of considerable current research. Dendritic multiarm polymers such as dendrimer, hyperbranched polymer, and star polymers are three dimensional macromolecules, in which a large number of linear arms of similar molecular weight and narrow molecular weight distribution emanate from a central core. (omitted)

• Proceedings of the Korean Information Science Society Conference
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• 2003.04a
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• pp.172-174
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• 2003

멀티미디어에 대한 사회적 욕구가 한층 커져감에 따라, 보다 고용량 고효율의 매체에 대한 연구도 활기차게 진행되어 왔다. 그리고 그 미디어에 적합한 파일시스템을 개발 하는 일 또한 꾸준히 진행되어 온 일이다. 여러 파일 시스템 중 하나인 UDF 는 DVD 매체를 위한 파일 시스템으로 사용되고 있다. 본 논문에서는 DVD 플래이어에 탑재하기 위해 삼성전자에서 개발한 ARM920T 마이크로 프로세서 코어를 사용하는 임베디드 시스템에 탑재될 실시간 운영체제를 위한 UDF 파일 시스템을 구현하였다. 이 UDF 파일 시스템은 가상 파일 시스템과 연동한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.143-149
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• 2020

Currently, a multi-core processor is mainly used as a central processing unit of a computer system, and a high-performance out-of-order processor is adopted as each core to maximize system performance. The early out-of-order execution processor with Tomasulo algorithm aimed at floating-point instructions, and it took several cycles to execute by the use of complex structures such as reorder buffer and reservation station. However, in order for the processor to properly utilize out-of-order execution and increase the throughput of instructions, it must operate in a fully pipelined manner. In this paper, a fully pipelined out-of-order processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, a program composed of ARM instructions is successfully performed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.6B
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• pp.325-333
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• 2007

An OS requires the device driver to control hardware IPs at application level. Development of a device driver requires specific acknowledge for target hardware and OS. In this paper, we present a system which generates a device driver together with an interface circuit. In the proposed system, an efficient device driver is generated by selecting a basic device driver skeleton, a function module code, and a header file table from the pre-constructed library and an interface circuit is constructed such that the generated device driver operates correctly. The proposed system is evaluated by generating a TFT-LCD device driver on the ARM922T core with 3.5 inch Samsung TFT-LCD in ARM-Linux environment. Experiment result shows that the writing time on the LCD is decreased by 1.12% and the compiled code size is increased by 0.17% compared to the manually generated one. The automatically generated device driver has no performance degradation in the latency of hardware control at the application program level. The system development time can be reduced using the proposed device driver generation system.

• The KIPS Transactions:PartA
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• v.10A no.4
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• pp.389-396
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• 2003

InfiniBand technology is being accepted as the future system interconnect to serve as the high-end enterprise fabric for cluster computing. This paper presents the design and implementation of the InfiniBand system interconnect, focusing on an InfiniBand host channel adapter (HCA) based on dual ARM9 processor cores The HCA is an SoC tailed KinCA which connects a host node onto the InfiniBand network both in hardware and in software. Since the ARM9 processor core does not provide necessary features for multiprocessor configuration, novel inter-processor communication and interrupt mechanisms between the two processors were designed and embedded within the KinCA chip. Kinch was fabricated as a 564-pin enhanced BGA (Bail Grid Array) device using 0.18${\mu}{\textrm}{m}$ CMOS technology Mounted on host nodes, it provides 10 Gbps outbound and inbound channels for transmit and receive, respectively, resulting in a high-performance cluster system.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.2
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• pp.227-242
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• 2022

This paper presents a Cache-Coherency Interconnect(CCI)-based Android pattern screen lock(PSL) attack on modern ARM processors. CCI has been introduced to maintain the cache coherency between the big core cluster and the little core cluster. That is, CCI is the central interconnect inside SoC that maintains cache coherency and shares data. In this paper, we reveal that CCI can be a side channel in security, that an adversary can observe security-sensitive operations. We design and implement a technique to compromise Android PSL within only a few attempts using the information of CCI in user-level applications on Android Nougat. Further, we analyzed the relationship between the pattern complexity and security. Our evaluation results show that complex and simple patterns would have similar security strengths against the proposed technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.102-116
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• 2009

There have been lots of researches for H.264/AVC performance enhancement on a multi-core processor. The enhancement has been performed through parallelization methods. Parallelization methods can be classified into a task-level parallelization method and a data level parallelization method. A task-level parallelization method for H.264/AVC decoder is implemented by dividing H.264/AVC decoder algorithms into pipeline stages. However, it is not suitable for complex and large bitstreams due to poor load-balancing. Considering load-balancing and performance scalability, we propose a horizontal data level parallelization method for H.264/AVC decoder in such a way that threads are assigned to macroblock lines. We develop a mathematical performance expectation model for the proposed parallelization methods. For evaluation of the mathematical performance expectation, we measured the performance with JM 13.2 reference software on ARM11 MPCore Evaluation Board. The cycle-accurate measurement with SoCDesigner Co-verification Environment showed that expected performance and performance scalability of the proposed parallelization method was accurate in relatively high level