• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.12-17
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• 2009

This paper presents a tag emulator for a UHF band RFID system. The tag emulator supports the 1800-6C and EPC global class 1 generation 2 standards. The transmitted signal from a reader is generated using the PIE coding and ASK modulation methods. Signals of a tag are from the FM0 coding and ASK modulation methods. The ARM7 processor carries out the overall control of the system and signal analysis of incoming data. The verification of the tag emulator employs the application platform implemented in C++. Users can define parameter values for protocol during the application run. The tag emulator presented in this paper allows evaluating various design alternatives of the target RFID system in real applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.40-47
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• 2007

For image processing hardware, including a face detecting engine, efficient constitution of external and internal memories is a consequential point because huge memory is required to store various signal processing filters and incoming images. In this paper, we modified a face detect algerian of a general filter method for efficient hardware design. In the hardware, several memory design techniques are presented for efficient handling of image data : re-accessing avoidance with minimized internal memory usage, residing frequently accessed memory and sequence memory accessing. The hardware which can process 25 frame image data per one second with 40KB internal memory was verified by using ARM(S3C2440A) and Virtex4 FPGA and it is being fabricated as a ASIC chip using Samsung CMOS 0.18um technology.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.

• Proceedings of the Korea Information Processing Society Conference
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• 2017.11a
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• pp.279-280
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• 2017

최근 ARM, Intel 등의 주요 CPU 제조사에서는 운영체제 등 상위 레벨 소프트웨어에 대한 공격으로부터 어플리케이션의 보안상 민감한 부분을 보호하려는 목적으로 신뢰실행환경(Trusted Execution Environment, TEE)이라는 격리된 실행 환경을 자사의 칩에 제공하고 있다. TEE를 활용하기 위해서는 일반 실행 환경에서 수행될 코드와 TEE에서 수행될 코드를 각각 작성하여야 한다. 본 논문에서는 TEE 프로그램 개발의 편의를 위해, 기존에 작성된 C 프로그램을 분석하여 보안상 민감한 정보를 처리하는 부분을 분석하는 도구를 제시한다. 개발자가 기존 C 프로그램에서 보안상 민감한 정보가 유입되는 부분을 표시하면 본 도구는 민감한 정보가 처리되는 함수 목록을 분석하고, 개발자는 이를 바탕으로 일반 실행 환경과 TEE에서 수행될 코드를 작성할 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2062-2068
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• 2008

In a u-City project in Busan, public transportation which is one of ITS has been considered. RFID system embedded with PXA255 chip and middleware capable of communicating a server side was developed. To perform data communication link with traffic card, developed system consists of wireless modules that are wireless LAN (IEEE802.11a/b and IEEE802.16. Using developed RFID system and middleware, it is expected that this system becomes a basic infrastructure to support a service of u-Traffic for u-City construction.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.3
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• pp.153-158
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• 2023

Domestically, the importance of system semiconductor design is increasing, and the balanced development with the high-end memory semiconductors should be promoted. Using Xilinx Vivado as a development enivronment tool, it reduces time and cost dramatically in implementing the processor on FPGA. In this paper, the VHDL language which provides record data structure for an efficient digital system design is used for designing a pipelined out-of-order superscalar processor. It has been simulated extensively, synthesized and implemented on FPGA and verified by Integrated Logic Analyzer. As a result, the pipelined out-of-order superscalar processor could be executed successfully.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.171-171
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• 2017

전산유체역학(CFD: Computational Fluid Dynamics)를 이용한 스마트팜 환경 내부의 정밀 제어 연구가 진행 중이다. 시계열 데이터의 난해한 동적 해석을 극복하기위해, 비선형 모델링 기법의 일종인 인공신경망을 이용하는 방안을 고려하였다. 선행 연구를 통하여 환경 데이터의 비선형 모델링을 위한 Tensorflow활용 방법이 하드웨어 가속 기능을 바탕으로 월등한 성능을 보임을 확인하였다. 그럼에도 오프라인 일괄(Offline batch)처리 방식의 한계가 있는 인공신경망 모델링 기법과 현장 보급이 불가능한 고성능 하드웨어 연산 장치에 대한 대안 마련이 필요하다고 판단되었다. CFD 해석을 위한 Solver로 SU2(http://su2.stanford.edu)를 이용하였다. 운영 체제 및 컴파일러는 1) Mac OS X Sierra 10.12.2 Apple LLVM version 8.0.0 (clang-800.0.38), 2) Windows 10 x64: Intel C++ Compiler version 16.0, update 2, 3) Linux (Ubuntu 16.04 x64): g++ 5.4.0, 4) Clustered Linux (Ubuntu 16.04 x32): MPICC 3.3.a2를 선정하였다. 4번째 개발환경인 병렬 시스템의 경우 하드웨어 가속는 OpenCL(https://www.khronos.org/opencl/) 엔진을 이용하고 저전력 ARM 프로세서의 일종인 옥타코어 Samsung Exynos5422 칩을 장착한 ODROID-XU4(Hardkernel, AnYang, Korea) SBC(Single Board Computer)를 32식 병렬 구성하였다. 분산 컴퓨팅을 위한 환경은 Gbit 로컬 네트워크 기반 NFS(Network File System)과 MPICH(http://www.mpich.org/)로 구성하였다. 공간 분해능을 계측 주기보다 작게 분할할 경우 발생하는 미지의 바운더리 정보를 정의하기 위하여 3차원 Kriging Spatial Interpolation Method를 실험적으로 적용하였다. 한편 병렬 시스템 구성이 불가능한 1,2,3번 환경의 경우 내부적으로 이미 존재하는 멀티코어를 활용하고자 OpenMP(http://www.openmp.org/) 라이브러리를 활용하였다. 64비트 병렬 8코어로 동작하는 1,2,3번 운영환경의 경우 32비트 병렬 128코어로 동작하는 환경에 비하여 근소하게 2배 내외로 연산 속도가 빨랐다. 실시간 CFD 수행을 위한 분산 컴퓨팅 기술이 프로세서의 속도 및 운영체제의 정보 분배 능력에 따라 결정된다고 판단할 수 있었다. 이를 검증하기 위하여 4번 개발환경에서 운영체제를 64비트로 개선하여 5번째 환경을 구성하여 검증하였다. 상반되는 결과로 64비트 72코어로 동작하는 분산 컴퓨팅 환경에서 단일 프로세서 기반 멀티 코어(1,2,3번) 환경보다 보다 2.5배 내외 연산속도 향상이 있었다. ARM 프로세서용 64비트 운영체제의 완성도가 낮은 시점에서 추후 성공적인 실시간 CFD 모델링을 위한 지속적인 검토가 필요하다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.60-64
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• 2004

In this paper, we implemented a real-time remote home monitoring system which we have ported the Linux OS and HTTP(Hypertext Transfer Protocol) web server. The GoAhead web server was ported using by ARM cross compiler. And then we used the analog to digital converter ADC0809 for sensing the vii able input signal at widely separated home. We have implemented linux device driver for ADC(Analog to Digital Convertor) and CGI-C(Common Gateway Interface - C language) application program using Client pull method for monitoring real-time changing data. The factor of monitoring is temperature, intensity of illumination and gas's existence. And this system has ability which check the status of out door and gas valve. We have designed the embedded web server system for home emergency monitoring in low cost.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.1
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• pp.51-58
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• 2013

As it is changing into aging society, rehabilitation, welfare and sports industry markets are being expanded fast. Especially, the field of vital signals interface to control welfare instruments like wheelchair, rehabilitation ones like an artificial arm and leg and general electronic ones is a new technology field in the future. Also, this technology can help not only the handicapped, the old and the weak and the rehabilitation patients but also the general public in various application field. The commercial bio-signal measurement instruments and interface systems are complicated, expensive and large-scaled. So, there are a lot of limitations for using in real life with ease. this thesis proposes a wireless transmission interface system that uses EMG(electromyogram) signals and a control module to manipulate hardware systems with portable size. We have designed a hardware module that receives the EMG signals occurring at the time of wrist movement and eliminated noises with filter and amplified the signals effectively. DSP(Digital Signal Processor) chip of TMS320F2808 which was supplied from TI company was used for converting into digital signals from measured EMG signals and digital filtering. We also have used PCA(Principal Component Analysis) technique and classified into four motions which have right, left, up and down direction. This data was transmitted by wireless module in order to display at PC monitor. As a result, the developed system obtains recognition success ratio above 85% for four different motions. If the recognition ratio will be increased with more experiments. this implemented system using EMG wrist direction signals could be used to control various hardware systems.