• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.1-6
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• 2010

H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a $4{\times}4$ sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and the requirement of high data bandwidth and high performance processing units. We propose adaptive pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. Parameters and coefficients are delivered using hand-shaking communication through dedicated interconnections and frame pixel data are transferred using AMBA AHB network. The processing time of each block is variable depending on the characteristics of images, and the processing units start to work whenever they are ready. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.

• The Journal of Korean Obstetrics and Gynecology
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• v.33 no.1
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• pp.36-58
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• 2020

Objectives: We conducted a literature study on the treatment trends in China to find out the possibility of Oriental medicine treatment of atypical hyperplasia of breast (AHB). Methods: RCTs (randomized controlled trial) on AHB were collected from CNKI (China National Knowledge Infrastructure). The search words were "乳腺增生", "乳腺囊性增生", "乳癖", "中医", "中药" and "中西医结合". The search period was limited from July 2006 to May 2017. Finally, we selected 107 RCTs which were clinical studies to find out the effectiveness of Chinese herbal medicine in comparison with Western medicine. After reviewing, we investigated Chinese herbal medication guide, Chinese treatment method and prescriptions. And the correlation between the treatments and the medicinal herbs was investigated to be useful in the clinical practice. Results: 1. The administration of herbal medicine was 58.9 percent in 63 cases, followed by menstrual cycles, and 41.1 percent in 44 cases, regardless of menstrual cycles. 2. In the basic frequency analysis between the treatment and the medicinal herb, the frequency of dissipate binds (散結) was the highest. Next, there was a high frequency of therapies such as activating blood-activating (活血), relieve pain (止痛), soothe the liver (疏肝), regulate qi (理氣), resolve phlegm (化痰), soften hardness (軟堅), resolve depression (解鬱), move qi (行氣) of frequency was high. In herbal medicine, bupleuri radix (柴胡), cyperi rhizoma (香附子), angelicae gigantis radix (當歸), fritillaria thunbergii bulb (貝母), paeoniae radix alba (白芍藥), prunellae spica (夏枯草), corydalis rhizoma (玄胡索) showed high frequency. 3. We finded out the correlation between the frequent treatment methods and the medicinal herbs using Text Mining. Conclusions: These findings are thought to help implement Korean traditional medicine treatments for AHB.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.5_6
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• pp.257-266
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• 2007

In On-Chip bus, the arbitration scheme is one of the critical factors that decide the overall system performance. The arbitration scheme used in traditional shared bus is the master-side arbitration based on the request and grant signals between multiple masters and single arbiter. In the case of the master-side arbitration, only one master and one slave can transfer the data at a time. Therefore the throughput of total bus system and the utilization of resources are decreased in the master-side arbitration. However in the slave-side arbitration, there is an arbiter at each slave port and the master just starts a transaction and waits for the slave response to proceed to the next transfer. Thus, the unit of arbitration can be a transaction or a transfer. Besides the throughput of total bus system and the utilization of resources are increased since the multiple masters can simultaneously perform transfers with independent slaves. In this paper, we implement and analyze the arbitration schemes for the Multi-Layer AHB BusMatrix based on the slave-side arbitration. We implement the slave-side arbitration schemes based on fixed priority, round robin and dynamic priority and accomplish the performance simulation to compare and analyze the performance of each arbitration scheme according to the characteristics of the master and slave. With the performance simulation, we observed that when there are few masters on critical path in a bus system, the arbitration scheme based on dynamic priority shows the maximum performance and in other cases, the arbitration scheme based on round robin shows the highest performance. In addition, the arbitration scheme with transaction based multiplexing shows higher performance than the same arbitration scheme with single transfer based switching in an application with frequent accesses to the long latency devices or memories such as SDRAM. The improvements of the arbitration scheme with transaction based multiplexing are 26%, 42% and 51%, respectively when the latency times of SDRAM are 1, 2 and 3 clock cycles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.126-133
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• 2006

This paper describes an AMBA-based IP to perform forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The function of the proposed IP based on AMBA Specification was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using $0.25{\mu}m$ standard cells and observed its correct operations on silicon.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.225-234
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• 2006

In this paper, we design a combined security processor, ECC, MD-5, and AES, as a SIP for cryptography of securing contents. Each SIP is modeled and designed in VHDL and implemented as a reusable macro through logic synthesis, simulation and FPGA verification. To communicate with an ARM9 core, we design a BFM(Bus Functional Model) according to AMBA AHB specification. The combined security SIP for a platform-based SoC is implemented by integrating ECC, AES and MD-5 using the design kit including the ARM9 RISC core, one million-gate FPGA. Finally, it is fabricated into a MPW chip using Magna chip $0.25{\mu}m(4.7mm{\times}4.7mm$) CMOS technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.390-398
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• 2004

This paper describes a study on the automatic generation system of the interface for communication among AMBA bus and IPs with different protocols. Employing an extended STG, the proposed system generates the interface modules required for the communication among IPs with different protocols. For an example system, the interface module for communication between AMBA AHB bus and a video decoder has been generated and verified in its functionality. The area and latency have been compared with the manually designed interface. For burst-mode communication, the generated interface module shows the comparable performance with the manually designed module. For single-mode communication, the generated interface module shows a slightly worse performance than the manually designed module. However, the increased area is negligible considering the size of the IP.

• Proceedings of the Safety Management and Science Conference
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• 2001.05a
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• pp.83-92
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• 2001

We consider some dependability management systems(IEC300, NASA AHB5300.1 and DIN VDE 0801) with reference on IEC300. Part I of IEC300(IEC300-1) covers the essential features of a comprehensive dependability programme for the planning, organization, direction, and control of resources to produce products which will be reliable and maintainable. We consider the contents of IEC300-1； scope, normative references, definitions, management responsibilities, product or project independent programme elements and project specific programme elements.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.658-660
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• 2003

본 논문에서는 AMBA 기반의 FPD 시스템에 적용 가능한 콘트라스트 컨트롤러를 설계 및 구현하였다. 제안한 콘트라스트 컨트롤러 내부에는 AMBA의 인터페이스 spec을 준수한 AMBA AHB 컨트롤러와 콘트라스트조정 블록, 메모리 컨트롤러. FPD 컨트롤러가 내장되어있다. 구현한 알고리즘은 실시간 처리가 가능하며 콘트라스트의 범위를 조정하는 가중치를 가진 알고리즘으로 기준되는 값을 이용하여 콘트라스트의 효율적인 조정이 가능하다. 콘트라스트 컨트롤러는 VHDL로 설계하였으며 FPGA를 이용한 H/W를 구현하여 TFT-LCD panel에 디스플레이 하여 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.105-116
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• 2008

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.