• Journal of Communications and Networks
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• v.18 no.3
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• pp.273-287
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• 2016

White-box cryptography presented by Chow et al. is an obfuscation technique for protecting secret keys in software implementations even if an adversary has full access to the implementation of the encryption algorithm and full control over its execution platforms. Despite its practical importance, progress has not been substantial. In fact, it is repeated that as a proposal for a white-box implementation is reported, an attack of lower complexity is soon announced. This is mainly because most cryptanalytic methods target specific implementations, and there is no general attack tool for white-box cryptography. In this paper, we present an analytic toolbox on white-box implementations of the Chow et al.'s style using lookup tables. According to our toolbox, for a substitution-linear transformation cipher on n bits with S-boxes on m bits, the complexity for recovering the $$O\((3n/max(m_Q,m))2^{3max(m_Q,m)}+2min\{(n/m)L^{m+3}2^{2m},\;(n/m)L^32^{3m}+n{\log}L{\cdot}2^{L/2}\}\)$$, where $m_Q$ is the input size of nonlinear encodings,$m_A$ is the minimized block size of linear encodings, and $L=lcm(m_A,m_Q)$. As a result, a white-box implementation in the Chow et al.'s framework has complexity at most $O\(min\{(2^{2m}/m)n^{m+4},\;n{\log}n{\cdot}2^{n/2}\}\)$ which is much less than $2^n$. To overcome this, we introduce an idea that obfuscates two advanced encryption standard (AES)-128 ciphers at once with input/output encoding on 256 bits. To reduce storage, we use a sparse unsplit input encoding. As a result, our white-box AES implementation has up to 110-bit security against our toolbox, close to that of the original cipher. More generally, we may consider a white-box implementation of the t parallel encryption of AES to increase security.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.852-855
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• 2005

This paper introduces a case study of designing a cryptographic processor dedicated to VPN/SSL system. The designed processor supports not only block cipher algorithm, including 3DES, AES, and SEED, but also 163 bit ECC public key crypto algorithm. Moreover, we adopted PCI Master interface in the design, which guarantees fast computation of cryptographic algorithm prevalent in general information security systems.

• Journal of Venture Innovation
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• v.2 no.1
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• pp.13-21
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• 2019

In LTE environment, which is 4th generation mobile communication systems, there is concern about private information exposure by transmitting initial identifier in plain text. This paper suggest mutual authentication protocol, which uses one-time password utilizing challenge-response and AES-based Milenage key generation algorithm, as solution for safe initial identification communication, preventing unique identification information leaking. Milenage key generation algorithm has been used in LTE Security protocol for generating Cipher key, Integrity key, Message Authentication Code. Performance analysis evaluates the suitability of LTE Security protocol and LTE network by comparing LTE Security protocol with proposed protocol about algorithm operation count and Latency.Thus, this paper figures out initial identification communication's weak points of currently used LTE security protocol and complements in accordance with traditional protocol. So, it can be applied for traditional LTE communication on account of providing additional confidentiality to initial identifier.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.16 no.5
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• pp.67-77
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• 2006

Radio Frequency IDentification (RFID) will soon become an important technology in various industries. Therefore, security mechanisms for Rm systems are emerging crucial problems in RFID systems. In order to guarantee privacy and security, it is desirable to encrypt the transferred data with a strong crypto algorithm. In this paper, we present the ultra-light weight Advanced Encryption Standard (AES) processor which is suitable for RFID tags. The AES processor requires only 3,992 logic gates and is capable of both 128-bit encryption and decryption. The processor takes 446 clock cycles for encryption of a 128-bit data and 607 clock cycles for decryption. Therefore, it shows 55% improved result in encryption and 40% in decryption from previous cases.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.115-117
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• 2022

Whitebox encryption technique is a method of preventing exposure of encryption keys by mixing encryption key information with a software-based encryption algorithm. Whitebox encryption technique is attracting attention as a technology that replaces conventional hardware-based security encryption techniques by making it difficult to infer confidential data and keys by accessing memory with unauthorized reverse engineering analysis. However, in the encryption and decryption process, a large lookup table is used to hide computational results and encryption keys, resulting in a problem of slow encryption and increased memory size. In particular, it is difficult to apply whitebox cryptography to low-cost, low-power, and light-weight Internet of Things products due to limited memory space and battery capacity. In addition, in a network environment that requires real-time service support, the response delay time increases due to the encryption/decryption speed of the whitebox encryption, resulting in deterioration of communication efficiency. Therefore, in this paper, we analyze whether the AES-based whitebox(WBC-AES) proposed by S.Chow can satisfy the speed and memory requirements based on the experimental results.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.132-134
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• 2004

This paper proposes partial image encryption system for secure transmission of images. Partial image encryption is suitable for real-time processing purpose of multimedia data that needs compression and encryption. Compression part uses modified SPIHT algorithm and encryption part uses AES. Partial image encryption is significant reduction in encryption time in comparison with whole image encryption.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1133-1136
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• 2003

This paper has been studied about the implemention of the data-encription processor and imformation security system. Also in the paper, the brief contents of the verification of the data-encryption algorithm and the method of using HDL-level sources implemented is described. And then this paper has been designed for multi-level data secure system to verify and analyze the data-encryption processor implemented as VHDL.

• Journal of Advanced Information Technology and Convergence
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• v.8 no.2
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• pp.1-11
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• 2018

Multimedia contents have been increasingly available over the Internet as wireless networks systems are continuously growing popular. Unlimited access from various users has led to unauthorized access of third parties or adversaries. This paper deals with the implementation of elliptic curve cryptography (ECC) based user authentication for securing multimedia contents over the Internet. The ECC technique has been incorporated with the advanced encryption standard (AES) algorithm to ensure the complexity of the proposed authentication scheme and to guarantee authenticity of multimedia services.

• Korean Journal of Acupuncture
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• v.25 no.2
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• pp.95-105
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• 2008

Objectives : This study is to establish the appropriate assessment of causalities from adverse events (AEs) which are related to acupuncture treatment. Methods : We assessed thirty AEs which were caused in the early phase trial on concomitant use of acupuncture and herbal medicines. We scored each AE on the questionnaire in Naranjo and SNU algorithm scale which are for drug causality assessment in pharmacoepidemiology. Results : In Naranjo scale, there were consistencies among the evaluators qualitatively with "Probable", "Possible" degree. In reliability test, parameters, such as, gamma and kendall's tau-b revealed the degrees of 73%, and 32%, respectively. There were disaccordant tendency in SNU algorithm scale. Conclusion : A new algorithm which reflects acupuncture properties should be developed and elucidated.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.