• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.253-255
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• 2017

본 논문에서는 IoT 디바이스의 인증암호를 위한 AES-GCM 암호코어를 설계하였다. AES-GCM 코어는 블록암호 AES와 GHASH 연산으로 기밀성과 무결성을 동시에 제공한다. 기밀성 제공을 위한 블록암호 AES는 운영모드 CTR과 비밀키 길이 128/256-bit를 지원한다. GHASH 연산과 AES 암호화(복호화)의 병렬 동작을 위해 소요 클록 사이클을 일치시켜 GCM 동작을 최적화 하였다. 본 논문에서는 AES-GCM 코어를 Verilog HDL로 모델링 하였고 ModelSim을 이용한 시뮬레이션 검증 결과 정상 동작함을 확인하였으며 Xilinx Virtex5 XC5VSX95T FPGA 디바이스 합성결과 4,567 슬라이스로 구현되었다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.171-173
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• 2016

128-비트의 마스터 키를 지원하는 블록암호 AES-128을 IoT 보안에 적합하도록 경량화하여 구현하였다. 키 스케줄러와 라운드 블록을 8 비트 데이터 패스로 구현하고, 다양한 최적화 방법을 적용함으로써 하드웨어를 최소화시켰으며, 100 MHz 클록 주파수에서 4,400 GE의 작은 게이트로 구현되었다. Verilog HDL로 설계된 AES 크립토 코어를 Vertex5 XC5VSX50T FPGA 디바이스에 구현하여 올바로 동작함을 확인하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.599-602
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• 2014

FPGA상에 AES 복호화 코어를 FIPS-197사양에 기술된 AES 알고리즘의 복호화부분을 구현하였다. 키값의 길이는 128/192/256비트를 지원하며, 별도의 코어 로직은 FPGA의 6-input lookup table의 이점을 살리도록 설계되었으며, 이결과로 2000개의 lookup table만을 이용하여 256비트 키에서 3Gbps의 처리가 가능하게 되었다. 코어는 난수 및 FIPS-197, SP-800a와 AESAVS사양의 테스트 벡터를 통해서 검증하였다.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.2
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• pp.327-334
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• 2016

Contrary to the common belief, DRAM which is used for the main memory of various computing devices retains its content even though it is powered-off. Especially, the data-retaining time can increase if DRAM is cooled down. The Cold Boot Attack, a kind of side-channel attacks, tries to recover the sensitive information such as the cryptographic key from the powered-off DRAM. This paper proposes a new algorithm which recovers the AES key under the symmetric-decay cold-boot-attack model. In particular, the proposed algorithm uses the strategy of reducing the size of the candidate key space by testing the randomness of the extracted AES key bit stream.

• Safety and Health at Work
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• v.13 no.4
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• pp.401-407
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• 2022

Background: The present study aimed to digitally evaluate the risk of overwork-related adverse effects (OrAEs) among employees from various occupational categories in Taiwan. Methods: Anonymous data of employees from seven companies/factories providing occupational health services were analyzed. The studied population comprised 5505 employees, and the data analyzed included employment duration, working hours, shift work schedules, and health checkup results. The risk for OrAEs was assessed by an index, Karo index (0-4, the larger the value, the higher the risk for OrAEs) obtained using a risk matrix made up of cardiocerebral and occupational risk factors. Karo index values of 3 and 4 were categorized as at high risk for OrAEs (h-OrAEs). Results: The 5505 employees had an average employment duration of 8.5 years and a mean age of 39.4 years. The prevalence rates for h-OrAEs of the seven companies/factories ranged from 3.9% to 34.2%. There were significant differences in prevalence rates for h-OrAEs between employees of retail stores and high-tech manufacturing factories. Multivariate analysis results indicated that workers of high-tech manufacturing factories had significantly higher risk for h-OrAEs compared with retail store workers. Conclusion: In terms of satisfying health risk management and legal requirements in Taiwan, the newly issued Karo index, which covers a wide range of occupational risk factors, can serve as an assessment and a warning tool for managing the risk of OrAEs in workplaces. To reduce risks for h-OrAEs, active and prudent control of cerebrocardiovascular risks and working hours is recommended.

• ETRI Journal
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• v.29 no.6
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• pp.820-822
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• 2007

ARIA and the Advanced Encryption Standard (AES) are next generation standard block cipher algorithms of Korea and the US, respectively. This letter presents an area-efficient unified hardware architecture of ARIA and AES. Both algorithms have 128-bit substitution permutation network (SPN) structures, and their substitution and permutation layers could be efficiently merged. Therefore, we propose a 128-bit processor architecture with resource sharing, which is capable of processing ARIA and AES. This is the first architecture which supports both algorithms. Furthermore, it requires only 19,056 logic gates and encrypts data at 720 Mbps and 1,047 Mbps for ARIA and AES, respectively.

• ETRI Journal
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• v.37 no.5
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• pp.1012-1022
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• 2015

Conventional cryptographic algorithms are not sufficient to protect secret keys and data in white-box environments, where an attacker has full visibility and control over an executing software code. For this reason, cryptographic algorithms have been redesigned to be resistant to white-box attacks. The first white-box AES (WB-AES) implementation was thought to provide reliable security in that all brute force attacks are infeasible even in white-box environments; however, this proved not to be the case. In particular, Billet and others presented a cryptanalysis of WB-AES with 230 time complexity, and Michiels and others generalized it for all substitution-linear transformation ciphers. Recently, a collision-based cryptanalysis was also reported. In this paper, we revisit Chow and others's first WB-AES implementation and present a conditional re-encoding method for cryptanalysis protection. The experimental results show that there is approximately a 57% increase in the memory requirement and a 20% increase in execution speed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.7
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• pp.1478-1482
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• 2003

In this paper. Rijndael cipher algorithm is implemented by a hardware. It was selected as the AES(Advanced Encryption Standard) by NIST. It has structure that round operation divided into 2 subrounds and subrounds are pipelined to calculate efficiently. It takes 5 clocks for one-round. The AES-128 cipher algorithm is implemented for hardware by ALTERA FPGA, and, analyzed the performance. The AES-128 cipher algorithm has approximately 424 Mbps encryption rate for 166Mhz max clock frequency. In case of decryption, it has 363 Mbps decryption rate fu 142Mhz max clock frequency. In case of cipher core, it has 320Mbps encryptionㆍdecryption rate for 125Mhz max clock frequency.

• International journal of thyroidology
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• v.11 no.2
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• pp.61-70
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• 2018

Tyrosine kinase inhibitors (TKIs) are widely used for the treatment of advanced radioiodine-refractory thyroid cancer. Although the previous studies including large-scale randomized controlled trials have demonstrated the effects of TKIs in advanced thyroid cancers, it has been found that most patients experienced adverse events (AEs). Unlike other cancers, even patients with advanced thyroid cancers are often asymptomatic. Rather, TKI use can make patients suffer adverse events. Therefore, the use of TKI should be decided after the full consideration of AEs as well as its efficacies. While using TKI, AEs should be monitored, evaluated, and managed appropriately, if AEs develop. In this review, the occurrence, evaluation, and management of AEs of sorafenib, lenvatinib, and vandetanib will be described, which TKIs are most commonly used for the treatment of advanced thyroid cancer. Some suggestions for the management of AEs in the real life are also provided.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.155-157
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• 2016

한국 표준 블록암호 알고리듬 ARIA(Academy, Research Institute, Agency)와 미국 표준인 AES(Advanced Encryption Standard) 알고리듬은 128-비트 블록 길이를 지원하고 SPN(substitution permutation network) 구조를 특징으로 가져 서로 유사한 형태를 지닌다. 본 논문에서는 ARIA와 AES를 선택적으로 수행하는 ARIA-AES 통합 프로세서를 효율적으로 구현하였다. Verilog HDL로 설계된 ARIA-AES 통합 프로세서를 Virtex5 FPGA로 구현하여 정상 동작함을 확인하였고, $0.18{\mu}m$ 공정의 CMOS 셀 라이브러리로 100KHz의 동작주파수에서 합성한 결과 39,498 GE로 구현되었다.