• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.44-50
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• 2004

In this paper, a DBM(Doubly Balanced Mixer) of 2 GHz is implemented on FR4 substrate. The structure of doubly balanced mixer requires, in general, two batons and a quad diode. For balun, a novel planar balun using microstrip to CPS is suggested and designed. The suggested balun shows the phase imbalance of 180$^{\circ}$${\pm}$ 1.5$^{\circ}$and the amplitude imbalance of ${\pm}$ 0.2 ㏈ for 1.5 to 2.5 GHz. Using the balun, DBM is succesfully implemented, and the measured conversion loss of up/down converter show about 6 ㏈ over the bandwidth. The balun may be applicable for MMIC DBM with the process supporting backside via thourgh more study.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.4
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• pp.119-125
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• 2022

The power supply for the anti-aircraft radar homing sensor should allow the system to receive power quickly and stably without the influence of noise. For this purpose, DC-DC converters are widely used for reliable power conversion. Also, switching of DC-DC converters Frequency noise should not cause false alarms and ghosts that may affect the detection and tracking performance of the system, and it should have a check function that can monitor power in real time while the homing sensor is operating. In order to apply to anti-aircraft radar homing sensor, we developed a multi-output switching power supply with maximum output 𐩒𐩒𐩒 W, efficiency 80% or more (@100% load), output power by receiving 28VDC input, and power supply to achieve more than 80% efficiency. A DC-DC converter was applied to this large output, and the multi-output flyback method was applied to the rest of the low-power output.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Geophysics and Geophysical Exploration
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• v.10 no.3
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• pp.203-210
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• 2007

As a part of basic studies on monitoring of landslides and slope stability using SP measurements, micro-electric potentials of rock samples were measured accompanied with the rock failure by a uniaxial loading test were measured. The measurement system consists of a 8 channel A/D converter with 24 bit resolution, uniaxial loading tester, strain gages and 4 sets of electrode attached to a rock sample. Rock samples of granite, limestone, and sandstone were tested. Also, mortar samples were tested in order to monitor electric-potentials of a uniform sample. Micro-electric potentials were detected in all saturated samples and the strength of them increased as the loading force increased. Sandstone samples showed the largest strength of micro-electric potential and it followed limestone and granite samples, which indicates a positive relationship with porosity of rocks. The mechanism generating these micro-electric potential can be explained in terms of electro-kinetics. In case of dry samples, micro-electric potential could be observed only in sandstone samples, where piezoelectric effect played main role due to high contents of quartz in sandstone samples. We found that biggest micro-electric potentials were observed at the electrodes near the crack surface of rock samples. This is very encouraging result that SP monitoring can be applied to predicting landsliding or to estimate collapsing position combining with monitoring of acoustic emissions.

• Journal of Advanced Marine Engineering and Technology
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• v.39 no.4
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• pp.483-488
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• 2015

This paper implements a long-term monitoring system (LMS) for ship's engine performance analysis (SEPA) based on the web, for the purpose of the communication speed and engine maintenance. This system is composed of a simulator, monitoring module with a multi channel A/D converter, monitoring computer, network attached storage (NAS), RS485 serial and wireless internet communication system. The existing products monitor the information transmitted from pressure sensors installed in the upper parts of each of engines in the local or web computer, but have a delay in the communication speed and errors in long-term monitoring due to the large volume of sampling pressure data. To improve these problems, the monitoring computer saves the sampling pressure data received from the pressure sensors in NAS, monitors the long-term sampling data generated by the sectional down sampling method on a local computer, and transmits them to the web for long-term monitoring. Because this method has one tenth of the original sampling data, it will use memory with small capacity, save communication cost, monitor the long-term sampling data for 30 days, and as a result, make a great contribution to engine maintenance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.613-623
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• 2000

Digital TV tuner for 8-VSB modulation was developed with satisfying the requirements of ATSC. The double frequency conversion and the active tracking filter in the front-end were used to reduce interference of the adjacent channels and multi-channels, which suppress If beat and image band. However, it was impossible to get frequency mapping between tracking filter and first VCO(Voltage Controlled Oscillator) in the double conversion digital TV tuner differing from conventional NTSC tuner. This paper, therefore, suggests the available structure and a new method for automatic frequency selection by obtaining the mapping of frequency characteristic over tracking voltage and the combined hardware which compose of Micro-controller, EEPROM, D/A(Digital-to-Analog Converter), OP amp and switch driver to solve above problems.

• Proceedings of the KSME Conference
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• 2000.11b
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• pp.150-155
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• 2000

Exhaust emissions from vehicles are the main source of air pollution. Many researchers are trying to find the way of reducing vehicle emissions, especially in the cold transient period of the FTP-75 test. In this study, UEGI (Unburned Exhaust Gas Ignition) technology, warming up the close-coupled catalytic converter (CCC) by igniting the unburned exhaust mixture using two glow plugs installed in the upstream of the catalyst, was developed. It was applied to an exhaust system with a hydrocarbon adsorber to ensure an effective reduction of HC emission during the cold start period. Results showed that the CCC reaches the light-off temperature (LOT) in a shorter time compared with the baseline exhaust system, and HC and CO emissions are reduced significantly during the cold start.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.861-862
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• 2015

In this paper we present a low area 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter). The proposed circuit is fabricated using Magnachip/SK Hynix 1-Poly 6-Metal $0.18-{\mu}m$ CMOS process, and it is powered by a 1.8-V supply. Total chip area is reduced by replacing the MIM capacitors with MOS capacitors instead of the capacitors consisting of overall part in chip area. The proposed circuit showed improved power dissipation of 1.9mW, and chip area of $0.45mm^2$ as compared to conventional research results at the power supply of 1.8V. The designed circuit also showed high SNDR (Signal-to-Noise Distortion Ratio) of 70.51dB, and excellent effective number of bits of 11.4bits.

• Journal of Advanced Navigation Technology
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• v.28 no.3
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• pp.348-355
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• 2024

A current source capable of stably supplying current as a measurement medium is required in order to measure and test important facilities that require large-scale measurement current, such as a control element drive mechanism control system(CEDMCS), in case of dismantling a nuclear power plant. However, it can provides only voltage power as a source, not current, although direct voltage controlled constant current source is essential to test major equipment. That kind of source is not available to supply stable constant current regardless of load variation. It is just voltage supplier. Developing current source is not easy other than voltage source. Very large-scale current source up to ampere class more than such ten times of normal current is inevitable to test above mentioned equipment. So, we developed large-scale current source which is controlled by input DC voltage and supplies constant stable current to object equipment according to this requirement. We measured and tested nuclear power plant equipment using given real site data for a long time and afforded long period load test, and then proved its validity and verification. The developed invetion will be used future installed important equipment measuring and testing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).