• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.61-69
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• 2010

In this paper, an 1.2V 8b 800MSPS A/D Converter(ADC) with an odd number of folding block to overcome the asymmetrical boundary-condition error is described. The architecture of the proposed ADC is based on a cascaded folding architecture using resistive interpolation technique for low power consumption and high input frequency. The ADC employs a novel odd folding block to improve the distortion of signal linearity and to reduce the offset errors. In the digital block, furthermore, we use a ROM encoder to convert a none-$2^n$-period code into the binary code. The chip has been fabricated with an $0.13{\mu}m$ 1P6M CMOS technology. The effective chip area is $870{\mu}m\times980{\mu}m$. SNDR is 44.84dB (ENOB 7.15bit) and SFDR is 52.17dBc, when the input frequency is 10MHz at sampling frequency of 800MHz.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.7
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• pp.2464-2479
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• 2014

Multi-view video coding is an international encoding standard that attains good performance by fully utilizing temporal and inter-view correlations. However, it suffers from high computational complexity. This paper presents a fast encoder design to reduce the level of complexity. First, when the temporal correlation of a group of pictures is sufficiently strong, macroblock-based inter-view prediction is not employed for the non-anchor pictures of B-views. Second, when the disparity between two adjacent views is above some threshold, frame-based inter-view prediction is disabled. Third, inter-view prediction is not performed on boundary macroblocks in the auxiliary views, because the references for these blocks may not exist in neighboring views. Fourth, finer partitions of inter-view prediction are cancelled for macroblocks in static image areas. Finally, when estimating the disparity of a macroblock, the search range is adjusted according to the mode size distribution of the neighboring view. Compared with reference software, these techniques produce an average time reduction of 83.65%, while the bit-rate increase and peak signal-to-noise ratio loss are less than 0.54% and 0.05dB, respectively.

• ETRI Journal
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• v.31 no.5
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• pp.585-592
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• 2009

This paper presents a method for decoding high minimal distance ($d_{min}$) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher$d_{min}$ than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high $d_{min}$, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-${\mu}m$ CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=$10^{-5}$ and is 44 percent smaller and consumes 28 percent less energy per decoded bit.

• Journal of Broadcast Engineering
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• v.15 no.4
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• pp.498-512
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• 2010

Intra coding is an indispensable coding tool since it can provide random accessibility as well as error resiliency. However, it is the problem that intra coding has relatively low coding efficiency compared with inter coding in the area of video coding. Even though H.264/AVC has significantly improved the intra coding performance compared with previous video standards, H.264/AVC encoder complexity is significantly increased, which is not suitable for low bit rate interactive services. In this paper, a Voting-based Intra Mode Bit Skip (V-IMBS) scheme is proposed to improve coding efficiency as well as to reduce encoding time complexity using decoder-side prediction. In case that the decoder can determine the same prediction mode as what is chosen by the encoder, the encoder does not send that intra prediction mode; otherwise, the conventional H.264/AVC intra coding is performed. Simulation results reveal a performance increase up to 4.44% overall rate savings and 0.24 dB in peak signal-to-noise ratio while the frame encoding speed of proposed method is about 42.8% better than that of H.264/AVC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• Journal of Advanced Information Technology and Convergence
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• v.8 no.2
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• pp.147-157
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• 2018

In this study, we analyzed an outdoor visible light communication system and implemented it through a simulation. We designed a Reed-Solomon encoder, a variable interleaver structure, and set it to the Institute of Electrical and Electronics Engineers (IEEE) 802.15.7 PHY I specification mode. We also analyzed the performance of an additive white gaussian noise (AWGN) channel environment using a root-raised-cosine (RRC) filter, implemented a MATLAB simulation and analyzed its performance. The results showed a requirement for an additional signal-to-noise ratio (SNR) of approximately 1.5 dB in a 3-ray multipath visible light channel environment than in an AWGN environment.

• The KIPS Transactions:PartB
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• v.11B no.6
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• pp.625-632
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• 2004

Since the H.264 encoding adopts both forward prediction and hi-direction prediction modes and exploits Variable Length Coding(VLC), the amount of data generated from video encoder varies as Flaying time goes by. The fixed bit rate encoding system which has limited transmission channel capacity uses a buffer to control output bitstream It's necessary to control the bitstream to maintain within manageable range so as to protect buffer from overflow or underflow. With existing bit amount control algorithms, the $\lambda_{MODE}$ which is relationship between distortion value and quantization parameter often excesses normal value to end up with video error. This paper proposes an algorithm to protect buffer from overflow or underflow by introducing a new quantization parameter against distortion value of H.264 video data. The test results of 6 exemplary data show that the proposed algorithm has the same PSNR as and up to 8% reduced bit rate against existing algorithms.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.121-130
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• 2007

In this paper, we propose a reversible watermarking scheme in the JPEG compression domain. The reversible watermarking is useful to authenticate the content without the quality loss because it preserves the original content when embed the watermark information. In the internet, for the purpose to save the storage space and improve the efficiency of communication, digital image is usually compressed by JPEG or GIF. Therefore, it is necessary to develop a reversible watermarking in the JPEG compression domain. When the watermark is embedded, the lossless compression was used and the original image is recovered during the watermark extracting process. The test results show that PSNRs are distributed from 38dB to 42dB and the payload is from 2.5Kbits to 3.4Kbits where the QF is 75. Where the QF of the Lena image is varied from 10 to 99, the PSNR is directly proportional to the QF and the payload is around $1.6{\sim}2.8Kbits$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.1
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• pp.141-150
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• 2010

In this paper, performance of a turbo-coded OFDM system is analyzed and simulated in a power line communication channel. Since the power line communication system typically operates in a hostile environment, turbo code has been employed to enhance reliability of transmitted data. The performance is evaluated in terms of bit error probability. As turbo decoding algorithms, MAP (maximum a posteriori), Max-Log-MAP, and SOVA (soft decision viterbi output) algorithms are chosen and their performances are compared. From simulation results, it is demonstrated that Max-Log-MAP algorithm is promising in terms of performance and complexity. It is shown that performance is improved 3dB by increasing the number of iterations, 2 to 8, and interleaver length of a turbo encoder, 100 to 5000. The results in this paper can be applied to OFDM-based high-speed power line communication systems.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.1-11
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• 1997

We developed a base station modulator ASIC for CDMA digital cellular system. In CDMA digital cellular system, the modulation is performed by convolutional encoding and QPSK with spread spectrum. The function blocks of base station modulator are CRC, convolutional encoder, interleaver pseudo-moise scrambler, power control bit puncturing, walsh cover, QPSK, gain controller, combiner and multiplexer. Each function block was designed by the logic synthesis of VHDL codes. The VHDL code was described at register transfer level and the size of code is about 8,000 lines. The circuit simulation and logic simulation were performed by COMPASS tools. The chip (ES-C2212B CMB) contains 25,205 gates and 3 Kbit SRAM, and its chip size is 5.25 mm * 5,45 mm in 0.8 mm CMOS cell-based design technology. It is packaged in 68 pin PLCC and the power dissipation at 10MHz is 300 mW at 5V. The ASIC has been fully tested and successfully working on the CDMA base station system.