• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.114-124
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• 2014

HEVC is a state-of-the-art video coding standard developed by JCT-VC. HEVC provides about 2 times higher subjective coding efficiency than H.264/AVC. One of the main goal of HEVC development is to efficiently coding UHD resolution video so that HEVC is expected to be widely used for coding UHD resolution video. Decoding such high resolution video generates a large number of memory accesses, so a decoding system needs high-bandwidth for memory system and/or internal communication architecture. In order to determine such requirements, this paper presents an analysis of the memory access complexity for HEVC decoder. we first estimate the amount of memory access performed by software HEVC decoder on an embedded system and a desktop computer. Then, we present the memory bandwidth models for HEVC decoder by analyzing the data flow of HEVC decoding tools. Experimental results show the software decoder produce 6.9-40.5 GB/s of DRAM accesses. also, the analysis reveals the hardware decoder requires 2.4 GB/s of DRAM bandwidth.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.28-34
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• 2015

Several parallelization methods that can be applied to High Efficiency Video Coding (HEVC) decoders are evaluated. The market requirements of high-resolution videos, such as Full HD and UHD, have been increasing. To satisfy the market requirements, several parallelization methods for HEVC decoders have been studied. Understanding these parallelization methods and objective comparisons of these methods are crucial to the real-time decoding of high-resolution videos. This paper introduces the parallelization methods that can be used in HEVC decoders and evaluates the parallelization methods comparatively. The experimental results show that the average speed-up factors of tile-level parallelism, wavefront parallel processing (WPP), frame-level parallelism, and 2D-wavefront parallelism are observed up to 4.59, 4.00, 2.20, and 3.16, respectively.

• Journal of Broadcast Engineering
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• v.19 no.6
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• pp.836-846
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• 2014

To expedite UHD (Ultra High Definition) video service, the HEVC (High-Efficiency Video Coding) technology has recently been standardized and it achieves two times higher compression efficiency than the conventional H.264/AVC. To obtain the improved efficiency, however, it employs many complex methods which need complicated calculation, thereby resulting in a significantly increased computational complexity when compared to that of H.264/AVC. For example, to improve the coding efficiency of intra frame coding, up to 35 intra prediction modes are defined in HEVC, but this results in an increased encoding time than the H.264/AVC. In this paper, we propose a fast intra prediction mode decision scheme which reduces computational complexity by changing the number of intra prediction mode in accordance with the percentage of PU sizes for a given video resolution, and by classifying the 35 intra prediction modes into 4 categories considering video resolution and quantization parameter. The experimental results show that the total encoding time is reduced by about 7% on average at the cost of only 2% increase in BD-rate.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.875-878
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• 2015

In this paper, we propose an intra prediction hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC encoder. The proposed intra prediction hardware architecture uses common operation units to reduce computational complexity and uses $4{\times}4$ block unit to reduce hardware area. In order to reduce operation time, common operation unit uses one operation unit to generate predicted pixels and filtered pixels in all prediction modes. Intra prediction hardware architecture introduces the $4{\times}4$ PU design processing to reduce the hardware area and uses intemal registers to support $32{\times}32$ PU processmg. The proposed hardware architecture uses ten common operation units which can reduce execution cycles of intra prediction. The proposed Intra prediction hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 41.5k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 150MHz, it can support 4K UHD video encoding at 30fps in real time, and operates at a maximum of 200MHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.11a
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• pp.4-6
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• 2014

본 논문에서는 하드웨어 HEVC 디코더의 움직임 보상 모듈의 구조를 제안한다. 제안된 구조를 갖는 움직임 보상 모듈은 하드웨어 처리 싸이클 수와 내부메모리 크기를 감소시키기 위해 하나의 코딩 유닛을 그보다 작은 여러 개의 블록으로 분할하여 처리할 수 있다. 제안된 움직임 보상 구조는 캐시를 통해 외부 메모리에 접근하여 참조 픽쳐를 로딩하는 단계와 보간 필터를 거쳐 예측 샘플을 생성하는 단계로 내부-파이프라인을 구성하며 코딩 유닛의 크기에 따라 내부-파이프라인에서 처리할 블록의 크기를 결정한다. 본 논문에서는 코딩 유닛 분할의 기준이 되는 블록 크기를 결정하기 위한 절충사항에 대해서도 논의한다. 제안된 구조의 효율성을 판단하기 위해 구현된 움직임 보상 모듈을 RTL 시뮬레이션 및 FPGA 보드 검증을 통해 테스트 하였으며, SoC 로 제작될 경우 초당 249 Mpixel 을 처리하여 4K-UHD 시퀀스의 실시간 디코딩이 가능한 것으로 판단되었다.

• Journal of Digital Contents Society
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• v.15 no.3
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• pp.425-432
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• 2014

4K high speed camera shooting enables shooting of fast subjects in Full HD 4 times resolution without motion blur due to increase in resolution and shutter speed. However, this shooting incurs several limitations including focus, intensity of radiation and increase in data quantity. As lack of intensity of radiation may occur due to increased shutter speed, it is shoot by opening aperture and limitation in focusing follows. In addition, there is limitation in shooting records since it has restriction in storage due to increased resolution and frame rate. In this regard, this study aims to analyze the limitations shown above through production case of 4K high speed camera (Phantom Flex 4K) and to design effective workflow to overcome this.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.66-69
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• 2016

In this paper, we suggests a Ka-band LNB considering next-generation UHD satellite TVRO. Since Ka-band has grater attenuation than Ku-band in atmosphere, we designed the low-noise down-converter to improve receiving sensitivity and to extend a dynamic range of receiver. It aims to compensate a quality of ultra high definition transmission signal for rainfall. The low-noise block diagram consists of a three-staged amplifier (LNA), band-pass filter for deleting image (BPF), mixer and IF when considering nonlinear characteristics in the receiver RF front end module. Also, we showed a LNB through optimization processes affecting dynamic range directly in receiver FEM. Asa resuly of experiment, the gain of low-noise down-converter show between 58.5dB and 60.7dB, the noise figure has a high characteristic as 1.38dB. Finally, the phase noise of local oscillator is -63.10dBc at 100MHz offset frequency.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.97-100
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• 2014

최근 초고화질 해상도(UHD) 영상 서비스에 따른 기존의 비디오 압축 기술인 H.264/AVC 대비 두 배 이상의 압축 성능을 가지는 HEVC(High-Efficiency Video Codec)의 표준화가 완료되었다. 그러나 높은 압축 효과를 얻기 위하여 복잡한 연산이 필요한 기법들이 많이 도입되어 HEVC의 부호화 복잡도는 H.264/AVC보다 크게 증가되었다. 예로써 HEVC의 화면내 예측 부호화는 예측 방향를 최대 35개까지 확장함으로써 기존 H.264/AVC에 비해서 향상된 부호화 효율을 갖지만 화면내 부호화의 복잡도는 크게 증가되어 복잡도 감소 기법이 필요하다. 본 논문은 화면내 예측 부호화에 사용되는 예측 방향 35가지를 비디오 해상도와 양자화 파라미터 크기를 고려하여 4가지 모드로 나누고 비디오 해상도의 따른 PU(Prediction Unit)의 크기의 점유율에 따라 예측 방향 개수를 변경함으로써 계산 복잡도를 감소시키는 기법을 제안한다. 실험 결과를 통해 제안된 기법을 적용함으로써 대략 2%의 BD-rate 증가로 부호화 시간을 4% 감소시킬 수 있었다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.4
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• pp.167-175
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• 2013

This study is the process of making high-definition TV broadcast color correction affects the end result comparison is focus on implement through study. In the production process and the impact on the color Correction in the video as an study for UHD, 4K, 6K video production workflow improvement of an effective program in the present and time and cost in the post production process, color correction for the final video through the production and overcome the failure of further in-efficient color correction study will help you to solve the problem. This study is the color changes over the course of the final video to see how much influence color correction of post-production. Color correction using a program of courses in Visual quality, regularly presented the possibility to retain and make on high definition video production post-production process for color correction method is utilized as the basis of study.

• Journal of Multimedia Information System
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• v.4 no.1
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• pp.19-26
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• 2017

The compression of video for both full HD and UHD requires the inclusion of extra vertical lines to every video frame, named as the DTV essential hidden area (DEHA), for the effective functioning of the MPEG-2/4/H encoder, stream, and decoder. However, while the encoding/decoding process is dependent on the DEHA, the DEHA is conventionally viewed as a redundancy in terms of channel utilization or storage efficiency. This paper proposes a block mode DEHA method to more effectively utilize the DEHA. Partitioning video block images and then evenly filling the representative DEHA macroblocks with the average DC coefficient of the active video macroblock can minimize the amount of DEHA data entering the compressed video stream. Theoretically, this process results in smaller DEHA data entering the video stream. Experimental testing of the proposed block mode DEHA method revealed a slight improvement in the quality of the active video. Outside of this technological improvement to video quality, the attractiveness of the proposed DEHA method is also heightened by the ease that it can be implemented with existing video encoders.