• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.10
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• pp.1361-1370
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• 2018

With the advent of OTT, the new concept of content delivery service is growing interest in the market, the development of appropriate equipment and application program is needed. In order to provide OTT service, a system to receive UHD broadcast to collect free content is needed. In this study, we designed an OTT service providing system that operates on 4K UHD video adapter hardware capable of IPTV service. First, we analyzed the situation to provide video free contents service and implemented a system to collect free contents. To validate the research and to make practical use of it, we have developed a mobile program for free content service and distributed it through the Google App Store. It is also installed in an OTT box with the ability to provide free content on the open market and is in service in several countries including Brazil.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.178-184
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• 2015

This paper proposes a hardware architecture for high performance Deblocking filter(DBF) in High Efficiency Video Coding for UHD(Ultra High Definition) videos. This proposed hardware architecture which has less processing time has a 4-stage pipelined architecture with two filters and parallel boundary strength module. Also, the proposed filter can be used in low-voltage design by using clock gating architecture in 4-stage pipeline. The segmented memory architecture solves the hazard issue that arises when single port SRAM is accessed. The proposed order of filtering shortens the delay time that arises when storing data into the single port SRAM at the pre-processing stage. The DBF hardware proposed in this paper was designed with Verilog HDL, and was implemented with 22k logic gates as a result of synthesis using TSMC 0.18um CMOS standard cell library. Furthermore, the dynamic frequency can process UHD 8k($7680{\times}4320$) samples@60fps using a frequency of 150MHz with an 8K resolution and maximum dynamic frequency is 285MHz. Result from analysis shows that the proposed DBF hardware architecture operation cycle for one process coding unit has improved by 32% over the previous one.

• TTA Journal
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• s.154
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• pp.100-105
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• 2014

• TTA Journal
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• s.154
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• pp.95-99
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• 2014

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.11a
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• pp.91-93
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• 2015

본 논문에서는 4K UHD(Ultra High Definition) 방송 수신기의 비디오 표준적합 및 에러 처리 평가를 위한 비디오 시험 스트림을 제안한다. 표준적합 시험 스트림은 4K UHD 방송 수신기의 비디오 압축 표준인 HEVC/H.265 의 표준 적합 여부를 판단하기 위해 사용이 가능하며, 에러 처리 평가 스트림은 비디오 스트림 내에 에러가 발생하였을 때 수신기가 에러를 처리하는 방식을 검증하기 위하여 사용 가능하다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.7
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• pp.1387-1394
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• 2015

Along with the development of network transmission technology, the IPTV market is growing in fast pace. Additionally the UHD resolution broadcasting system along with user experience (UX) that provides better service to user has attracted attention recently since there are not enough research has been done with differentiated the UX that can enhance the UX yet. Therefore we proposed a low complexity syntax level image stitching implementation technique that run with multi-view services, which makes possibility to view multiple channel or video contents on the screen at the same time. Simulation results have demonstrated the liability and effectiveness of the proposed algorithm by showing that capability of generating more than 80 frames per second by stitching four Full-HD size videos into UHD frame.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• Journal of Satellite, Information and Communications
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• v.12 no.4
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• pp.11-17
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• 2017

In this paper, we propose the authoring tools engine supported a 4 dimension display contents which serve display of high quality (UHD*250) curved using 4 dimension engine, which is a innovation technology by authoring tools of management software supported 4 dimension editing environment on curved flexible display. The important technology is as follows, the first, the authoring tools of 4 dimension viedo wall for a flexible high quality display(UHD*256) using multiscreen synchornization, the second implemented a bidirection interaction technology of UI/UX interface, which is established by 360 degree recognition sensor for digital signage, the 4 dimension viedowall flexible display with curve, the third, implemented the authoring tool software for various dimension electronic books first in the world.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.469-471
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• 2022

This paper presents an implementation of a calibration circuit to correct the gain error, DC offset and sampling clock phase error generated in the process of converting digital pixels to analog pixels to drive an analog-driven 4K UHD LCOS panel. The proposed calibration circuit consists of a gain and DC offset adjustment circuit and a sampling clock phase adjustment circuit. The calibration circuit is implemented with an FPGA device, and video amplifiers.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.11a
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• pp.57-58
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• 2009

최근 MPEG에서 HD(High Definition) 해상도 이상의 초고해상도 비디오를 위한 HVC(High-performance Video Coding) 표준화에 대하여 논의가 되고 있다. 이런 흐름 속에서 ETRI에서 보유중인 베리어 방식의 CCD를 사용하여 NHK에서 제작된 RG1G2B 4K 영상은 dark current error, bias error, flat error 등에 의한 영상 자체의 열화가 많아 HVC 연구를 위한 영상으로 사용되기에는 무리가 많다. 가장 이상적인 해결방안은 NHK에서 제작한 카메라 자체에 열화제거를 위한 장치들을 설치하여 규칙적인 열화를 제거한 영상을 확보하는 것이지만, 특수 제작된 카메라여서 이 방법은 불가능하다. 본 논문은 이 NHK의 영상을 wavelet 기반의 denoise filter를 응용하여 영상의 열화를 일정부분 제거하면서 영상의 디테일이 최대한 유지되도록 하여, 기존의 영상보다 깔끔한 8K UHD 영상을 획득하는 방안을 제시한다.