• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집E
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• pp.548-554
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• 2001

A GA(Genetic Algorithm) based 3D-PTV technique has been developed. The measurement system consists of three CCD cameras, Ar-ion laser, an image grabber and a host computer. The fundamental of the developed technique was based on that one-to-one correspondence is found between two tracer particles selected at two different image frames taking advantage of combinatorial optimization of the genetic algorithm. The fitness function controlling reproductive success in the genetic algorithm was expressed by a kind of continuum theory on the sparsely distributed particles in space. In order to verify the capability of the constructed measurement system, a performance test was made using the LES data set of an impinging jet. The developed 3D-PTV system was applied to the measurement of flow characteristics of the wake of a circular cylinder.

• 한국멀티미디어학회논문지
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• 제9권1호
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• pp.41-50
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• 2006

이 연구는 현재 툴 제공 업체 수준에서 지원이 미미한 PDA 플랫폼의 3D 그래픽 소프트웨어 엔진의 실효성을 개선시키고 그래픽 엔진의 핵심 부분인 래스터라이져의 성능 향상을 목적으로 진행되었다. 상대적으로 약한 프로세싱 파워를 가진 플랫폼에서 소프트웨어로 3D 그래픽 엔진을 구현하는 것은 많은 문제점이 있으나, 우리는 현재 널리 사용되고 있는 깊이정렬 알고리즘과 Z-버퍼 알고리즘의 장점을 취하고 문제점을 보완하여 적응형 Z-버퍼 알고리즘을 구현하고 여러 가지 PDA 플랫폼들을 사용하여 실험하였다. 새로운 알고리즘의 속도는 두 알고리즘의 중간 정도로 나타났으며, 깊이정렬 알고리즘과는 달리 순서 역전에 따른 오류가 발생하지 않음을 확인하였다.

• 한국멀티미디어학회논문지
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• 제5권5호
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• pp.552-561
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• 2002

본 논문은 쾌속조형(rapid prototyping) 시스템에서 사용되며 3D 기하학적 형상을 가지는 STL 파일에 워터마크를 삽입하고 추출하는 방법에 관한 연구이다. 제안된 알고리즘은 3D 형상의 왜곡이 없도록 하기위해, 패싯의 법선 영역과 꼭지점 영역에 워터마크를 삽입한다. 워터마크 비트들은 법선의 위치와 꼭지점의 순서 정보를 이용하여 삽입된다 제안된 알고리즘은 패싯의 저장 순서에 대한 종속성이 없으며, 워터마크의 비가시성 (invisibility)을 충족한다. 제안된 알고리즘으로 3D 기하학적 형상에 워터마크를 삽입하고 추출하는 실험 결과들은 STL로 표현된 3D원형상에 영향을 주지 않고 워터마크의 삽입과 추출이 가능함을 보여준다.

• 한국정보과학회논문지:시스템및이론
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• 제35권3호
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• pp.133-140
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• 2008

본 논문은 GPU상에서 작동되는 ray tracing을 위한 효과적인 k-D tree 탐색 알고리즘을 제안한다. 기존의 k-D tree를 위한 GPU 기반 탐색 알고리즘은 임의의 단말노드에서 교차되는 primitive를 찾지 못한 경우. root 노드 방향으로 bottom-up 탐색하여 부모 노드에서 bounding box 교차검사를 이용해 형제 노드의 기 방문 여부를 판단한다. 이러한 방법은 이미 방문한 부모 노드의 방문과 bounding box 교차검사를 중복적으로 수행한다. 본 논문에서 제안하는 알고리즘은 bottom-up 탐색을 수행 할 때 형제노드가 이전에 방문했는지를 확인할 수 있는 효율적인 방법을 제시함으로써 형제노드 및 부모로드의 방문을 생략하도록 하고, 또한 아직 방문하지 않은 노드에 대해서만 bounding box 교차검사를 수행함으로써 중복된 연산을 피한다. 결과적으로 본 논문의 실험은 기존 알고리즘 대비 제안하는 알고리즘이 약 30%의 성능 향상이 있음을 보여 준다.

• 대한건축학회연합논문집
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• 제21권4호
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• pp.15-26
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• 2019

In recent years, researchers are increasingly trying to use BIM-based 3D models for BIM nD design such as 4D (3D + Time) and 5D (4D + Cost). However, there are still many problems in efficiently using process management based on the BIM information created at each design stage. Therefore, this study proposes a method to automate 4D and 5D design support in each design stage by using BIM-based Dynamo algorithm. To do this, I implemented an algorithm that can automatically input the process information needed for 4D and 5D by using Revit's Add-in program, Dynamo. In order to support the 4D design, the algorithm was created to enable automatic process simulation by synchronizing process simulation information (Excel file) through the Navisworks program, BIM software. The algorithm was created to automatically enable process simulation. And to support the 5D design, the algorithm was developed to enable automatic extraction of the information needed for mass production from the BIM model by utilizing the dynamo algorithm. Therefore, in order to verify the 4D and 5D design support algorithms, we verified the applicability through consultation with related workers and experts. As a result, it has been demonstrated that it is possible to manage information about process information and to quickly extract information from design and design changes. In addition, BIM data can be used to manage and input the necessary process information in 4D and 5D, which is advantageous for shortening construction time and cost. This study will make it easy to improve design quality and manage design information, and will be the foundation for future building automation research.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1991년도 한국자동제어학술회의논문집(국제학술편); KOEX, Seoul; 22-24 Oct. 1991
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• pp.1939-1943
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• 1991

Path planning is an important task for optimal motion of a robot in structured or unstructured environment. The goal of this paper is to plan the shortest collision-free path in 3D, when a robot is navigated to pick up some tools or to repair some parts from various locations. To accomplish the goal of this paper, the Path Coordinator is proposed to have the capabilities of an obstacle avoidance strategy[3] and a traveling salesman problem strategy(TSP)[23]. The obstacle avoidance strategy is to plan the shortest collision-free path between each pair of n locations in 2D or in 3D. The TSP strategy is to compute a minimal system cost of a tour that is defined as a closed path navigating each location exactly once. The TSP strategy can be implemented by the Neural Network. The obstacle avoidance strategy in 2D can be implemented by the VGraph Algorithm. However, the VGraph Algorithm is not useful in 3D, because it can't compute the global optimality in 3D. Thus, the Path Coordinator is proposed to solve this problem, having the capabilities of selecting the optimal edges by the modified Genetic Algorithm[21] and computing the optimal nodes along the optimal edges by the Recursive Compensation Algorithm[5].

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제14권8호
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• pp.763-767
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• 2008

본 논문에서는 모바일 환경에서의 3D 그래픽 처리에 효과적인 고성능/저전력의 CORDIC 구조를 구성하기 위하여 각도 기반 검색(ABS)과 스케일링 효과를 고려한 검색(SCS)과 같은 두 가지 오프라인 벡터링 방법을 제안하고 이를 통해 연산의 반복횟수를 줄이는 알고리즘을 개발한다. ABS 알고리즘은 3차원 벡터를 두 각으로 표현하고 이를 검색의 기준으로 삼았고, SCS 알고리즘은 단위 벡터를 기준으로 하여 벡터 회전 시에 최소의 반복 연산만으로도 원하는 회전을 수행할 수 있는 최적의 기본각 회전 시퀀스를 오프라인으로 미리 검색하여 적용한다 본 논문에서 제안하는 ABS, SCS 알고리즘을 통해 지연을 각각 50% 감소시킬 수 있었으며, 이와 함께 voltage scaling 기술을 적용하여 전력 소모를 크게 감소시킬 수 있음을 논의한다.

• 대한전자공학회논문지
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• 제24권6호
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• pp.1068-1073
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• 1987

Traditional circuit partitioning algorithm using the cluster development method, which is suitable for such applications as single chip floor planning or multiple layer PCB system placement, where the clusters are formed so that inter-cluster nets are localized within the I/O connector pins, may not be appropriate for the functiona block placement in truly 3-D electronic modules. 3-D hybrid IC is one such example where the inter-layer routing as well as the intra-layer routing can be maximally incorporated to reduce the overall circuit size, cooling requirements and to improve the speed performance. In this paper, we propose a new algorithm called MBE(Minimum Box Embedding) for the layer assignment of each functional block in 3-D hybrid IC design. The sequence of MBE is as follows` i) force-directed relaxation in 3-D space, ii) exhaustive search for the optimal orientation of the slicing plane and iii) layer assignment. The algorithm is first explaines for a 2-D reduced problem, and then extended for 3-D applications. An example result for a circuit consisting of 80 blocks has been shown.

• 한국멀티미디어학회논문지
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• 제20권12호
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• pp.1951-1959
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• 2017

Due to the fact that 3D printing is applied to many areas of life, 3D printing models are often used illegally without any permission from the original providers. This paper presents a novel watermarking algorithm for the copyright protection and ownership identification for 3D printing based on the radius curvature of 3D triangle. 3D triangles are extracted and classified into groups based on radius curvature by the clustering algorithm, and then the mean radius curvature of each group will be computed for watermark embedding. The watermark data is embedded to the groups of 3D triangle by changing the mean radius curvature of each group. In each group, we select a 3D triangle which has the nearest radius curvature with the changed mean radius curvature. Finally, we change the vertices of the selected facet according to the changed radius curvature has been embedded watermark. In experiments, the distance error between the original 3D printing model and the watermarked 3D printing model is approximate zero, and the Bit Error Rate is also very low. From experimental results, we verify that the proposed algorithm is invisible and robustness with geometric attacks rotation, scaling and translation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.75-78
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• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.