• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• Korean Chemical Engineering Research
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• v.55 no.6
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• pp.816-821
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• 2017

An integrated slow mixing/sedimentation and net fit fiber filtration system has been developed to reduce the high concentrations of suspended solid (SS) and total phosphorus (T-P) in the reject water from sewage/wastewater. A filtration device used in this experiment consists of coagulation, in-line mixing, air injection, slow mixing/sedimentation, and filtration processes. The performance test using this device was carried out with six operational modes for reject water from sewage treatment plant. Experimental conditions used were 16.7, 33.3, 41.7 and 50.0 ton/day of flow rate and 2~4 of Al/P molar ratio. By injection of coagulant in each operational mode, the high removal efficiencies of SS and T-P were obtained, but continuous operation time was decreased to 7.8~11.4 min in most modes. However, when the Mode 5 of the developed filtration device was applied, the continuous operation time was maintained up to 88.2 min. Also, it was found that the continuous operation time in the Mode 5 using the developed system was increased from 8 to 11.3 times longer than those in other modes. Backwashing flow rate was also very low at 5.4% of total filtered water. Therefore, it can be concluded that the Mode 5 of the developed filtration system was the most efficient treatment method for the removal of high concentrations of SS and T-P.

• Journal of the Korean GEO-environmental Society
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• v.15 no.2
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• pp.5-15
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• 2014

Target reliability index in the limit state design indicated the safety margin and it is important to determine the partial factor. To determine the target reliability index which is needed in the limit state design, the six design and construction case histories of gravel compaction piles (GCP) were investigated. The limit state functions were defined by bulging failure for the major failure mode of GCP. The reliability analysis were performed using the first order reliability method (FORM) and the reliability index was calculated for each ultimate bearing capacity formulation. The reliability index of GCP tended to be penportional to the safety factor of allowable stress design and average value was ${\beta}$=2.30. Reliability level that was assessed by reliability analysis and target reliability index for existing structure foundations were compared and analyzed. As a result, The GCP was required a relatively low level of safety compared with deep and shallow foundations and the currd t reliability level were similar to the target reliability in the reinforced earth retaining-wall and soil-nailing. Therefore the target reliability index of GCP suggested as ${\beta}_T$=2.33 by various literatures together with the computed reliability level in this study.

• The Journal of the Acoustical Society of Korea
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• v.41 no.3
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• pp.278-286
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• 2022

In this study, a 33-mode Free-Flooded Ring (FFR) transducer was designed to apply piezoelectric single crystal PIN-PMN-PT, which has high piezoelectric constants and electromechanical coupling coefficient. To ensure low-frequency high transmitting sensitivity characteristics with a small size of FFR transducer, the commercial FFR transducer based on piezoelectric ceramics was compared. To develop the FFR transducer with broadband characteristics, a piezoelectric segmented ring structure inserted with inactive elements was applied. The oil-filled structure was applied to minimize the change of acoustic characteristics of the ring transducer. It was verified that the transmitting voltage response, underwater impedance, and beam pattern matched the finite element numerical simulation results well through an acoustic test. The difference in the transmitting voltage response between the measured and the simulated results is about 1.3 dB in cavity mode and about 0.3 dB in radial mode. The fabricated FFR transducer had a higher transmitting voltage response compared to the commercial transducer, but the diameter was reduced by about 17 %. From this study, it was confirmed that the feasibility of a single crystal-applied FFR transducer with compact size and high-power characteristics. The effectiveness of the performance prediction by simulation was also confirmed.

• Journal of the Earthquake Engineering Society of Korea
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• v.16 no.3
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• pp.23-33
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• 2012

Dynamic response measurements from natural excitation were carried out for three 18-story office buildings to determine their inherent properties. The beam-column frame system was adopted as a typical structural form, but a core wall was added to resist the lateral force more effectively, resulting in a mixed configuration. To extract modal parameters such as natural frequencies, mode shapes and damping ratios from a series of vibration records at each floor, the most advanced operational system identification methods based on frequency- and time-domain like FDD, pLSCF and SSI were applied. Extracted frequencies and mode shapes from the different identification methods showed a greater consistency for three buildings, however the three lower frequencies extracted were 1.2 to 1.7 times as stiff as those obtained using the initial FE models. Comparing the extracted fundamental periods with those estimated from the code equations and FE analysis, the FE analysis results showed the most flexible behavior, and the most simple equation that considers the building height as the only parameter correlated fairly well with test results. It is recognized that such a discrepancy arises from the fact that the present tests exclude the stiffness decreasing factors like concrete cracking, while the FE models ignore the stiffness increasing factors, such as the contribution of non-structural elements and the actual material properties used.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.33-40
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• 2005

This paper describes a design of FFT/IFFT Core(FFT256/2k), which is an essential block in terrestrial DMB modem. It has four operation modes including 256/512/1024/2048-point FFT/IFFT in order to support the Eureka-147 transmission modes. The hybrid architecture, which is composed of R2SDF and R2SDC structure, reduces memory by $62\%$ compared to R2SDC structure, and the SQNR performance is improved by TS_CBFP(Two Step Convergent Block Floating Point). Timing simulation results show that it can operate up to 50MHz(a)2.5-V, resulting that a 2048-point FFT/IFFT can be computed in 41-us. The FFT256/2k core designed in Verilog-HDL has about 68,400 gates and 58,130 RAM. The average power consumption estimated using switching activity is about 113-mW, and the total average SQNR of over 50-dB is achieved. The functionality of the core was fully verified by FPGA implementation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.263-269
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• 2017

A piezoelectric cantilever energy harvester (PCEH) driven in longitudinal (3-3) vibration mode was fabricated, and its electrical properties were evaluated by varying the resistive load. A commercial PZT piezoelectric ceramic with a high piezoelectric charge constant ($d_{33}$) of 520 pC/N and the interdigitated (IDT) electrode pattern was used to fabricate the PCEH driven in longitudinal vibration. The IDT Ag electrode embedded piezoelectric laminates were co-fired at $850^{\circ}C$ for 2 h. The 3-3 mode PCEH was successfully fabricated by attaching the piezoelectric laminates to a SUS304 elastic substrate. The PCEH exhibited a high output power of 3.8 mW across the resistive load of $100k{\Omega}$ at 100 Hz and 1.5 G. This corresponds to a power density of $10.3mW/cm^3$ and a normalized global power factor of $4.56mW/g^2{\cdot}cm^3$. Given the other PCEH driven in transverse (3-1) vibration mode, the 3-3 mode PCEH could be better for vibration energy harvesting applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.8B
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• pp.667-680
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• 2008

In this work, we present the results of our empirical study on 802.11 wireless LAN network traffic. We collect the packet trace from existing campus wireless LAN infra-structure. We analyzed four different data sets: aggregate traffic, upstream traffic, downstream traffic, tcp only packet trace from aggregate traffic. We analyze the time series aspect of underlying traffic (byte count process and packet count process), marginal distribution of time series, and packet size distribution. We found that in all four data sets there exist long-range dependent property in byte count and packet count process. Inter-arrival distribution is well fitted with Pareto distribution. Upstream traffic, i.e. from the user to Internet, exhibits significant difference in its packet size distribution from the rests. Average packet size of upstream traffic is 151.7 byte while average packet size of the rest of the data sets are all greater than 260 bytes. Packets with full data payloads constitutes 3% and 10% in upstream traffic and the downstream traffic, respectively. Despite the significant difference in packet size distribution, all four data sets have similar Hurst values. The Hurst alone does not properly explain the stochastic characteristics of the underlying traffic. We model the underlying traffic using fractional-ARIMA (FARIMA) and fractional Gaussian Noise (FGN). While the fractional Gaussian Noise based method is computationally more efficient, FARIMA exhibits superior performance in accurately modeling the underlying traffic.

• 대한공업교육학회지
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• v.33 no.2
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• pp.312-324
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• 2008

To improve the newly designed HKS(hinge kit system) in common refrigerators, it was investigated the new robust methodologies. There were the study of failure modes, mechanisms in the marketplace, and the design parameters of HKS with various improvements using accelerated life testing. Based on the claimed marketplace product returns and 1st ALT reproduction, the fracturing and cracking occur in the housing of the HKS. The missing design parameters of the failed HKS in the design phase of the refrigerator was the housing hinge kit structure. The corrective action plans are the modifications of the housing hinge kit structure from the open supporting to all supporting structure. Based on 2nd ALTs, the fracturing and cracking occur in the torsion shaft. The missing design parameter was the roundness of torsion shaft. After a sequence of ALT testing, the levels of the missing design parameters were setup. The yearly failure rate and B1 life of the redesigned HKS, based on the results of ALT, were over 0.01 percent and 10 years, respectively. The parameter design through the inspection of the failed product, load analysis, and three rounds of ALT, was very effective in the new robust design methodologies of the mechanical system and this method can be applied to other design system.

• The Journal of the Acoustical Society of Korea
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• v.20 no.6
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• pp.34-39
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• 2001

An adaptive multi-rate (AMR) speech coder was adopted as a standard of W-CDMA by 3GPP and ETSI. The AMR coder is based on the CELP algorithm operating at rates ranging from 12.2 kbps down to 4.75 kbps, and it is a source controlled codec according to the channel error conditions and the traffic loading. In this paper, we implement the DSP S/W of the AMR coder using OakDSPCore. The implementation is based on the CSD17C00A chip developed by C&S Technology, and it is tested using test vectors, for the AMR speech codec, provided by ETSI for the bit exact implementation. The DSP B/W requires 20.6 MIPS for the encoder and 2.7 MIPS for the decoder. Memories required by the Am coder were 21.97 kwords, 6.64 kwords and 15.1 kwords for code, data sections and data ROM, respectively. Also, actual sound input/output test using microphone and speaker demonstrates its proper real-time operation without distortions or delays.