• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.3 no.1
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• pp.63-69
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• 2010

In this paper, a new design method of asymmetrical configuration of main amplifier and peaking amplifier using changed bias point is proposed for excellent linearity, instead of the conventional Doherty structure. We have utilized the uneven wilkinson power divider for the unequal power drive at the input network of amplifiers. And we proposed a compensating method of the decreasing efficiency due to improving linearity using 3-stage Doherty structures. From the simulation results of asymmetrical Dohertry power amplifier and asymmetrical 3-stage Doherty power amplifier with uneven power drive are implemented. From the implementation and measurement results of the each amplifier, IMD characteristics have -55 dBc as the good efficiency of 13% compensates the decreased entire efficiency due to the improving linearity characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.813-822
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• 2009

We have investigated operation of a 1:2:2 asymmetric 3-stage Doherty PA(Power Amplifier) and implemented using the Freescale's 4 W, 10 W PEP LDMOSFETS at 1 GHz. By employing the three peak efficiency characteristics, compared to the two peak N-way Doherty PA, the asymmetric 3-stage Doherty can overcome the serious efficiency degradation along the backed-off output power region and maximize the average efficiency for the modulation signal. To maximize the efficiency characteristic, the inverse class F PA has been designed as carrier and peaking amplifiers. Furthermore, to extract the proper load modulation operation, the adaptive gate bias control signal has been applied to the two peaking PAs based on the envelope tracking technique. For the 802.16e Mobile WiMAX(World Interoperability for Microwave Access) signal with 8.5 dB PAPR(Peak to Average Power Ratio), the proposed Doherty PA has shown 55.46 % of high efficiency at an average output power of 36.85 dBm while maintaining the -37.23 dB of excellent RCE(Relative Constellation Error) characteristic. This is the first time demonstration of applying the saturated PA and adaptive gate bias control technique to the asymmetric 3-stage Doherty PA for the highly efficient transmitter of the base-station application.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.399-404
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• 2014

A power amplifier (PA) for a femto-cell base station should be highly efficient, linear and small. The efficiency for amplification of a high peak-to-average power ratio (PAPR) signal was improved by designing an asymmetric Doherty PA (DPA). The linearity was improved by applying third-order inter-modulation (IM3) cancellation method. A small size is achieved by designing the DPA using GaN MMIC process. The implemented 2-stage DPA delivers a power-added efficiency (PAE) of 38.6% and a gain of 33.4 dB with an average power of 34.2 dBm for a 7.2 dB PAPR 10 MHz bandwidth LTE signal at 2.14 GHz.

• Journal of Advanced Navigation Technology
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• v.12 no.3
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• pp.220-226
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• 2008

This paper proposes the Reconfigurable Doherty Amplifier(RDA) with asymmetric structure which has ${\lambda}/4$ impedance transformer for modulating the load impedance in peaking amplifier path. This structure is possible to implement a compact size for N-stage multi Doherty amplifier and to get almost same characteristics that is compared to conventional Doherty amplifier. To realize the high efficiency amplifier, we were implemented 45 Watts power amplifier at transmitter band of Wideband Code Division Multiple Access(WCDMA) base-station. As a result, in case of WCDMA 1 Frequency Allocation(FA) input signals, this amplifier has obtained a 26.3% Power Added Efficiency(PAE) at 8 dB back-off point from P1dB and an Adjacent Channel Leakage Power(ACLR) is -40.4 dBc at center frequency ${\pm}5MHz$ deviation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.339-345
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• 2016

This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.