• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.5
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• pp.27-33
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• 1993

This paper describes the hardware implementation of 2-D FIR digital filter for a real-time image processing. Generally, the most time-consuming operation in signal processing is the multiplication operation. To avoid it in digital filter. Pelid and Liu proposed the distributed arithmetic method for the one-dimensional case. The implementation method proposed in this paper is to extend Pelid's method to two-dimensional FIR filter using simple ROM lookup table and to use the technique of pipe lining two main operations of memory access and arithmetic. As a result, the speed of our proposed hardware implementation is two times faster than that of conventional methods and can be close to the real time speed.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.7_8
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• pp.359-369
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• 2003

We present efficient generalized algorithms for all-to-all personalized communication operations in a 2D torus. All-to-all personalized communication, or complete exchange, is at the heart of numerous applications, such as matrix transposition, Fast Fourier Transform(FFT), and distributed table lookup. Some algorithms have been Presented when the number of nodes is power-of-2 or multiple-of-four form, but there has been no result for general cases yet. We first present complete exchange algorithm called multiple-Hop-2D when the number of nodes is in the form of multiple-of-two. Then by extending this algorithm, we present two algorithms for an arbitrary number of nodes. Split-and-Merge algorithm first splits the whole network into zones. After each zone performs complete exchange, merge is applied to finish the desired complete exchange. By handling extra steps in Double-Hop-2D algorithm, Modified Double-Hop-2D algorithm performs complete exchange operation for general cases. Finally, we compare the required start-up time for these algorithms.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1429-1439
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• 2019

Buck-Boost LLC (BBLLC) converters based on a PWM + phase control strategy are good candidates for high efficiency, high power density and wide input range applications. Nevertheless, they suffer from large computational complexity when it comes to calculating the optimal phase for ZVS of all the switches. In this paper, a method is proposed for a microcontroller unit (MCU) to calculate the optimal phase quickly and accurately. Firstly, a 2-D lookup table of the phase is established with an index of the input voltage and output current. Then, a bilinear interpolation method is applied to improve the accuracy. Meanwhile, simplification of the phase equation is presented to reduce the computational complexity. When compared with conventional curve-fitting and LUT methods, the proposed method makes the best tradeoff among the accuracy of the optimal phase, the computation time and the memory consumption of the MCU. Finally, A 350V-420V input, 24V/30A output experimental prototype is built to verify the proposed method. The efficiency can be improved by 1% when compared with the LUT method, and the computation time can be reduced by 13.5% when compared with the curve-fitting method.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.464-474
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• 2000

All-to-all personalized communication, or complete exchange, is at the heart of numerous applications, such as matrix transposition, fast Fourier Transform(FFT), and distributed table lookup.We present an efficient all-to-all personalized communication algorithm for a 2D torus inwormhole-routed networks. Our complete exchange algorithm adopts divide-and-conquer approach toreduce the number of start-up latency significantly, which is a good metric for network performancein wormhole networks. First, we divide the whole network into 2x2 basic cells, After speciallydesignated nodes called master nodes have collected messages to transmit to the rest of the basic cell,only master nodes perform complete exchange with reduced network size, N/2 x N/2. When finishedwith this complete exchange in master nodes, these nodes distribute messages to the rest of the masternode, which results in the desired complete exchange communication. After we present our algorithms,we analyze time complexities and compare our algorithms with several previous algorithms. And weshow that our algorithm is efficient by a factor of 2 in the required start-up time which means thatour algorithm is suitable for wormhole-routed networks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}