• Title/Summary/Keyword: 2D interconnects

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Electromigration Characteristics Stduy DCV Interconnect Structures in Cu Dual-Damascene Process (Cu Dual Damascene 배선 공정에서의 DCV 배선구조의 EM 특성 연구)

  • Lee, Hyun-Ki;Choi, Min-Ho;Kim, Nam-Hoon;Kim, Sang-Yong;Chang, Eui-Goo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2005.07a
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    • pp.123-124
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    • 2005
  • We investigated the effect of a Ta/TaN Cu diffusion barrier existence on the reliability and the electrical performance of Cu dual-damascene interconnects. A high EM performance in Cu dual-damascene structure was observed the BCV(barrier contact via) interconnect structure to remain Ta/TaN barrier layer. Via resistance was decreased DCV interconnect structure by bottomless process. This structure considers that DCV interconnect structure has lower activation energy and higher current density than BCV interconnect structure. The EM failures by BCV via structure were formed at via hole, but DCV via structure was formed EM fail at the D2 line. In order to improve the EM characteristic of DCV interconnect structure by bottomless process, after Ta/TaN diffusion barrier layer in via bottom is removed by Ar+ resputtering process, it is desirable that Ta thickness is thickly made by Ta flash process.

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Effect of Bonding Process Conditions on the Interfacial Adhesion Energy of Al-Al Direct Bonds (접합 공정 조건이 Al-Al 접합의 계면접착에너지에 미치는 영향)

  • Kim, Jae-Won;Jeong, Myeong-Hyeok;Jang, Eun-Jung;Park, Sung-Cheol;Cakmak, Erkan;Kim, Bi-Oh;Matthias, Thorsten;Kim, Sung-Dong;Park, Young-Bae
    • Korean Journal of Materials Research
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    • v.20 no.6
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    • pp.319-325
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    • 2010
  • 3-D IC integration enables the smallest form factor and highest performance due to the shortest and most plentiful interconnects between chips. Direct metal bonding has several advantages over the solder-based bonding, including lower electrical resistivity, better electromigration resistance and more reduced interconnect RC delay, while high process temperature is one of the major bottlenecks of metal direct bonding because it can negatively influence device reliability and manufacturing yield. We performed quantitative analyses of the interfacial properties of Al-Al bonds with varying process parameters, bonding temperature, bonding time, and bonding environment. A 4-point bending method was used to measure the interfacial adhesion energy. The quantitative interfacial adhesion energy measured by a 4-point bending test shows 1.33, 2.25, and $6.44\;J/m^2$ for 400, 450, and $500^{\circ}C$, respectively, in a $N_2$ atmosphere. Increasing the bonding time from 1 to 4 hrs enhanced the interfacial fracture toughness while the effects of forming gas were negligible, which were correlated to the bonding interface analysis results. XPS depth analysis results on the delaminated interfaces showed that the relative area fraction of aluminum oxide to the pure aluminum phase near the bonding surfaces match well the variations of interfacial adhesion energies with bonding process conditions.

Development of kW Class SOFC Systems for Combined Heat and Power Units at KEPRI

  • Lee, Tae-Hee;Choi, Jin-Hyeok;Park, Tae-Sung;Yoo, Keun-Bae;Yoo, Young-Sung
    • Journal of the Korean Ceramic Society
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    • v.45 no.12
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    • pp.772-776
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    • 2008
  • The Korea Electric Power Research Institute (KEPRI) has been developing planar solid oxide fuel cells (SOFCs) and power systems for combined heat and power (CHP) units. The R&D work includes solid oxide fuel cell (SOFC) materials investigation, design and fabrication of single cells and stacks, and kW class SOFC CHP system development. Anode supported cells composed of Ni-YSZ/FL/YSZ/LSCF were enlarged up to $15{\times}15\;cm^2$ and stacks were manufactured using $10{\times}10\;cm^2$ cells and metallic interconnects such as ferritic stainless steel. The first-generation system had a 37-cell stack and an autothermal reformer for use with city gas. The system showed maximum stack power of about $1.3\;kW_{e,DC}$ and was able to recover heat of $0.57{\sim}1.2\;kW_{th}$ depending on loaded current by making hot water. The second-generation system was composed of an improved 48-cell stack and a prereformer (or steam reformer). The thermal management subsystem design including heat exchangers and insulators was also improved. The second-generation system was successfully operated without any external heat source. Under self-sustainable operation conditions, the stack power was about $1.3\;kW_{e,DC}$ with hydrogen and $1.2\;kW_{e,DC}$ with city. The system also recuperated heat of about $1.1\;kW_{th}$ by making hot water. Recently KEPRI manufactured a 2kW class SOFC stack and a system by scaling up the second-generation 1kW system and will develop a 5kW class CHP system by 2010.

Effect of Ag Nanolayer in Low Temperature Cu/Ag-Ag/Cu Bonding (저온 Cu/Ag-Ag/Cu 본딩에서의 Ag 나노막 효과)

  • Kim, Yoonho;Park, Seungmin;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.28 no.2
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    • pp.59-64
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    • 2021
  • System-in-package (SIP) technology using heterogeneous integration is becoming the key of next-generation semiconductor packaging technology, and the development of low temperature Cu bonding is very important for high-performance and fine-pitch SIP interconnects. In this study the low temperature Cu bonding and the anti-oxidation effect of copper using porous Ag nanolayer were investigated. It has been found that Cu diffuses into Ag faster than Ag diffuses into Cu at the temperatures from 100℃ to 200℃, indicating that solid state diffusion bonding of copper is possible at low temperatures. Cu bonding using Ag nanolayer was carried out at 200℃, and the shear strength after bonding was measured to be 23.27 MPa.

A Study on Wafer-Level 3D Integration Including Wafer Bonding using Low-k Polymeric Adhesive (저유전체 고분자 접착 물질을 이용한 웨이퍼 본딩을 포함하는 웨이퍼 레벨 3차원 집적회로 구현에 관한 연구)

  • Kwon, Yongchai;Seok, Jongwon;Lu, Jian-Qiang;Cale, Timothy;Gutmann, Ronald
    • Korean Chemical Engineering Research
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    • v.45 no.5
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    • pp.466-472
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    • 2007
  • A technology platform for wafer-level three-dimensional integration circuits (3D-ICs) is presented, and that uses wafer bonding with low-k polymeric adhesives and Cu damascene inter-wafer interconnects. In this work, one of such technical platforms is explained and characterized using a test vehicle of inter-wafer 3D via-chain structures. Electrical and mechanical characterizations of the structure are performed using continuously connected 3D via-chains. Evaluation results of the wafer bonding, which is a necessary process for stacking the wafers and uses low-k dielectrics as polymeric adhesive, are also presented through the wafer bonding between a glass wafer and a silicon wafer. After wafer bonding, three evaluations are conducted; (1) the fraction of bonded area is measured through the optical inspection, (2) the qualitative bond strength test to inspect the separation of the bonded wafers is taken by a razor blade, and (3) the quantitative bond strength is measured by a four point bending. To date, benzocyclobutene (BCB), $Flare^{TM}$, methylsilsesquioxane (MSSQ) and parylene-N were considered as bonding adhesives. Of the candidates, BCB and $Flare^{TM}$ were determined as adhesives after screening tests. By comparing BCB and $Flare^{TM}$, it was deduced that BCB is better as a baseline adhesive. It was because although wafer pairs bonded using $Flare^{TM}$ has a higher bond strength than those using BCB, wafer pairs bonded using BCB is still higher than that at the interface between Cu and porous low-k interlevel dielectrics (ILD), indicating almost 100% of bonded area routinely.