• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.5
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• pp.515-525
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• 2014

In this paper, we present a design and implementation of a Voltage-tuned Planar Composite Resonator Oscillator(Vt-PCRO) with a low phase noise. The designed Vt-PCRO is composed of a resonator, two phase shifters, and an amplifier. The resonator is designed using a dual mode SIW(Substrate Integrated Waveguide) resonator and has a group delay of about 40 nsec. Of the two phase shifters (PS1 and PS2), PS1 with a phase shift of $360^{\circ}$ is used for the open loop gain to satisfy oscillation condition without regard to the electrical lengths of the employed microstrip lines in the loop. PS2 with a phase shift of about $70^{\circ}$ is used to tune oscillation frequency. The amplifier is constructed using two stages to compensate for the loss of the open loop. Through the measurement of the open loop gain, the tune voltage of the PS1 can be set to satisfy the oscillation condition and the loop is then closed to form the oscillator. The oscillator with a oscillation frequency of 5.345 GHz shows a phase noise of -130.5 dBc/Hz at 100 kHz frequency offset. The oscillation power and the electrical frequency tuning range is about 3.5 dBm and about 4.2 MHz for a tuning voltage of 0~10 V, respectively.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.1-5
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• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.490-496
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• 2007

This paper describes the design and implementation of an integrated LTCC front-end module for the IEEE802.11a WLAN applications by performing the behavioral-level simulation using measurement-based behavioral model. To meet the IEEE802.11a WLAN standard, a system transmitting 1024 symbols through 64-QAM process at the rate of 54Mbps should be implemented and nonlinear properties are confirmed by simulations of ACPR and EVM in this circumstance. The right offsets of ACPR which are 30MHz, 20MHz, and 11MHz distant from the center frequency of 5.8GHz are 49.36dBc, 36.90dBc, and 24.58dBc, respectively. The left offsets are 50.14dBc, 30.04dBc, and 28.85dBc, respectively and EVM is 2.94%. The size of the module implemented with LTCC five-layer substrates is $13.4mm{\times}14.2mm$. The measured characteristics of the transmitter show P1dB of 16.2dBm and power gain of 16.73dB. Those of the receiver exhibit the small signal gain of 16.24dB and noise figure of 7.83dB.