• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.381-391
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• 2010

In this paper, a novel frequency reconfigurable active array antenna(RAA) system, which can be reconfigurable for three reconfigurable frequency bands, is proposed by using commercial RF MEMS switches. The MEMS switch shows excellent insertion loss, linearity, as well as isolation. So, the system performance degradation of the reconfigurable system by using MEMS switches can be minimized. The proposed frequency reconfigurable active antenna system is consisted with the noble frequency reconfigurable front-end amplifiers(RFA) with the simple reconfigurable impedance matching circuits(RMC), reconfigurable antenna elements(RAE), as well as a reconfiguration control board(RCB) for MEMS switch control. The proposed RAA system can be reconfigurable for three frequency bands, 850 MHz, 1.9 GHz, and 3.4 GHz, with $2{\times}2$ array of the RAE having broadband printed dipole antenna topology. The validity of the proposed RFA as well as RAA is also presented with the experimental results of the fabricated systems.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.813-822
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• 2009

We have investigated operation of a 1:2:2 asymmetric 3-stage Doherty PA(Power Amplifier) and implemented using the Freescale's 4 W, 10 W PEP LDMOSFETS at 1 GHz. By employing the three peak efficiency characteristics, compared to the two peak N-way Doherty PA, the asymmetric 3-stage Doherty can overcome the serious efficiency degradation along the backed-off output power region and maximize the average efficiency for the modulation signal. To maximize the efficiency characteristic, the inverse class F PA has been designed as carrier and peaking amplifiers. Furthermore, to extract the proper load modulation operation, the adaptive gate bias control signal has been applied to the two peaking PAs based on the envelope tracking technique. For the 802.16e Mobile WiMAX(World Interoperability for Microwave Access) signal with 8.5 dB PAPR(Peak to Average Power Ratio), the proposed Doherty PA has shown 55.46 % of high efficiency at an average output power of 36.85 dBm while maintaining the -37.23 dB of excellent RCE(Relative Constellation Error) characteristic. This is the first time demonstration of applying the saturated PA and adaptive gate bias control technique to the asymmetric 3-stage Doherty PA for the highly efficient transmitter of the base-station application.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.12
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• pp.1172-1175
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• 2011

In this paper, a design method of multi-tone signals for the measurement of adjacent-channel power-ratios on power amplifiers is suggested. Because most tests for power amplifiers in production are performed with single-tone signals, its testing accuracy is not guaranteed as the signal complexity increases. Therefore, the application of multi-tone signals to the testing is suggested by optimized complex coefficients of each tones for the best statistical similarity to the original modulated signal. From the verification, a 802.11a signal was replaced with a multi-tone signal of N=10, with the complex coefficients generated by the suggested method. The resulting measurements on the ACLR of 2.4 GHz power amplifier showed successful accuracy of less than 1 dB discrepancy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.7 s.337
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• pp.1-4
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• 2005

A four-channel photoreceiver ways have been realized in a 0.8$\mu$m Si/SiGe HBT technology for the applications of parallel optical interconnects. The receiver array includes four-channel transimpedance amplifiers (TIAs) and p-i-n photodiodes, where the TIAs exploit a common-emitter (CE) input configuration. Measured results demonstrate that the four-channel CE TIA array provides 3.9GHz bandwidth, 62dB$\Omega$ transimpedance gain, 7.5pA/sqrt(Hz) average noise current spectral density, and less than -25dB crosstalk between adjacent channels with 40mW power dissipation.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.19-25
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• 2008

In this paper, the front end module (FEM) was proposed for 2.4GHz WLAN band by LTCC multilayer application. The FEM was composed of power amplifier IC, switch IC, and LTCC module. LTCC module consists of output matching circuit and lowpass filter as Tx part, bandpass filter as Rx part. Design of output matching circuit for LTCC was used matching parameter from output matching circuit based on lumped circuit on the PCB board. The dielectric constant of LTCC substrate is 9. The substrate was composed of total 26 layers with each 30um thickness. Ag paste was used for the internal pattern as the conductor material. The size of the module is $4.5mm{\times}3.2mm{\times}1.4mm$. The fabricated FEM showed the gain of 21dB, ACPR of less than -31dBc first side lobe and Less than -59dBc second side lobe and the output power of 23Bm at P1dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.159-168
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• 2012

In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.181-184
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• 2002

본 논문에서는 600Hz 무선 LAN 시스템에 탑재를 위한 600㎓ 대역 전력증폭기 모듈을 개발 하였다. 600㎓ 대역 전력증폭기 모듈에 실장된 600㎓ 대역 전력증폭기 MMIC는 ETRI에서 설계 및 제작한 것으로 칩의 크기는 2.80 × 1.75㎟이며, on-wafer측정을 하여 얻은 결과는 동작 주파수 58~620Hz에서 소신호 이득은 12.4dB이고, 최대 소신호 이득은 59~60G보z에서 ISdB이며, 출력전력(Pldn)은 16.3~16.7dBm을 얻었다. 이와 같은 특성을 갖는 전력증폭기 MMIC를 사용하여 모듈을 제작하였으며, RF feed line을 위해 Rogers 사의 R03003 기판을 사용하였다. 모듈의 입출력은 동작 주파수 대역에 적합한 WRl5라는 waveguide 형태를 사용하였고, DC 바이어스 공급을 위해 3.5㎜ K-connector를 사용하였다 제작한 모듈의 크기는 40 × 30 × 15㎣이며, 최적의 성능을 얻고자 tuning bar를 상하로 이동하여 최적점을 찾았으며 나사로 고정하여 상태를 유지하도록 하였다. DC 바이어스 및 RF feed line과 칩의 연결은 본딩에 의한 인덕턴스를 최소화하기 위하여 3mil 두께의 리본 본딩을 하였다 전력증폭기 모듈을 측정한 결과, 동작주파수 600㎓ 대에서 소신호 이득은 6dB 이상, 입력 정합은 -lOdB 이하, 출력 정합은 -4dB 이하로 측정되었긴, 출력전력은 SdBm 이상으로 측정되었다. 동국대에서 제작한 600Hz 무선 LAN 시스템에 전력증폭기 모듈을 시스템 송신부에 탑재 시험한 결과, 동영상을 실시간으로 전송하는데 성공하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.