• Journal of electromagnetic engineering and science
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• 제3권1호
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• pp.39-44
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• 2003

An unconditionally stable compact 2D Alternating-Direction Implicit (ADI) FDTD method for calculating dispersion characteristics of waveguide structures is proposed. The numerical stability and numerical dispersion relation of the proposed method are also presented and discussed. Numerical wavelengths for the dominant and higher order modes in a hollow waveguide are obtained from numerical simulations and compared with those from the analytical dispersion relation. The numerical results show that the proposed scheme has the potential to successfully analyze a class of waveguides having locally fine geometry with reduced numerical costs.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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• pp.519-523
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• 2004

In this paper, a simple power control scheme of Class-D inverter, which is varied duty cycle of fixed frequency to desired output power. It is more suitable and acceptable for high-frequency induction heating (IH) jar applications. The proposed control scheme has the advantages of not only wide power regulation range but also ease to control output power. Also it can achieve the stable and efficient Zero-Voltage-Switching (ZVS) in whole load range. The control principles of proposed method are described in detail and its validity is verified trough simulations results on 38.5kHz IGBT for induction heating rated on 1.6kW with constant frequency variable power.

• 전자공학회논문지D
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• 제34D권11호
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• pp.83-89
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• 1997

An optimize delectroabsorption modulator structure is designed for high speed optical communication systems considering the extinction efficiency, operating bandwidth, polarization loss, and wavelength chirping. the operating wavelength region is $1.55\mu\textrm{m}$ and the deep ridge structure is adapted for th eminimum polarization loss. Simulations show that the absorption layer thickness larger than $0.25\mu\textrm{m}$, and the modulator length shorter than $200\mu\textrm{m}$ are required for the bandwidth over 10GHz. To obtain the modulatiron efficiency over 10dB/V, a wavelength detuning needs to be determined less than 40meV.

• 천문학회보
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• 제43권1호
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• pp.38.3-38.3
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• 2018

The properties of unseen high-redshift sources (and sinks) are encoded in the 3D structure of the cosmic 21-cm signal. Here I introduce a flexible parametrization for high-z galaxies' properties, including their star formation rates, ionizing escape fraction and their evolution with the mass of the host dark matter halos. With this parametrization, I self-consistently calculate the corresponding 21-cm signal during reionization and the cosmic dawn. Using a Monte Carlo Markov Chain sampler of 3D simulations, 21CMMC, I demonstrate how combining high-z luminosity functions with a mock 21-cm signal can break degeneracies, resulting in ~ percent level constraints on early universe astrophysics.

• 전자공학회논문지A
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• 제33A권11호
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• pp.152-161
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• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1351-1353
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• 2000

In this paper, it is proposed to constant power control of solar power system. The solar power system has disadvantage that low power density and variable power output. Proposed strategy is controled by DC/DC converter using phase shift PWM and I-PD type control applying type 1 digital system. The validity of proposed control strategy is verified from simulations results using PSIM.

• 한국CDE학회논문집
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• 제12권1호
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• pp.39-49
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• 2007

Recently three-dimensional (3-D) die design and production process has been widely introduced into the tooling shops of automotive manufacturers to reduce time-to-production of brand-new automobiles. 3-D solid models created in CAD systems are used not only for various simulations for design verification, but also for NC tool path generation to machine dies and their Styrofoam patterns. However, a lot of time and cost will be required to build solid models for dies if designers use only the generalized modeling capabilities of commercial 3-D CAD systems. To solve this problem, it is necessary to customize 3-D CAD system for the specific die design and manufacturing process. This paper describes a dedicated 3-D CAD system based on Unigraphics for die design for automotive body panels. The system provides not only 3-D design capabilities, but also standard part libraries, to enhance design productivity. The design process modeling technology has been introduced to facilitate redesign of the die for the modified panel. By introducing this system, dies can be designed more rapidly in the 3-D space, and their solid data can be directly transferred to CAM tools for NC tool path generation and simulation tools for virtual manufacturing.

• Progress in Superconductivity
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• 제4권2호
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• Environmental Engineering Research
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• 제23권4호
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• pp.442-448
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• 2018

This paper presents the numerical simulation of advection-diffusion mechanism of BOD concentration which was used as an indicator of waste only in one flow-direction of waste stabilization ponds (1-dimension (1-D)). This model was represented in partial differential equation order 2. The purpose of this paper was to determine the simulation of the model 1-D of wastewater transport phenomena based advection-diffusion mechanism and did validate the model. Numerical methods which was used for the solution of this model is finite difference method with Forward Time Central Space scheme. The simulation results which was obtained would be compared with field observation data as a validation model. Collection of field data was carried out in the Wastewater Treatment Plant Sewon, Bantul, D.I. Yogyakarta. The results of numerical simulations were indicate that the advection-diffusion mechanism takes place continuously over time. Then validation of the model was state that there was a difference between the calculation results with the field data, with a correlation value of 0.998.

• 한국인터넷방송통신학회논문지
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• 제18권6호
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• pp.127-132
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• 2018

본 논문에서는 W-대역에서 동작하는 고이득 캐스코드 혼합기를 설계 및 제작하였다. W-대역과 같이 높은 주파수 대역에서는 소자의 성능저하로 인해 혼합기의 변환손실이 커지게 된다. 이는 송수신단 구성 시 RF 버퍼 증폭기와 같은 추가적인 이득을 줄 수 있는 회로의 추가로 이어지고 이는 시스템 전체의 선형성 및 안정성에 영향을 미친다. 따라서 혼합기 설계 시 변환이득을 최대화하는 설계가 필요하다. 본 논문에서는 혼합기의 변환이득을 최대화하는 것에 초점을 두고 높은 변환이득을 얻기 위해 혼합기의 바이어스를 최적화하였고, 로드-풀 시뮬레이션을 이용하여 출력 정합회로를 최적화하였다. 설계된 회로는 $0.1-{\mu}m$ GaAs pHEMT 공정을 이용하여 제작하였고, 측정을 통해 성능을 검증하였다. 제작된 회로는 W-대역에서 -4.7 dB의 최대 변환이득과 2.5 dBm의 입력 1-dB 감쇄 전력이 측정되었다.