• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.9A
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• pp.1101-1107
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• 2004

This paper presents an optimization algorithm and technique for designing parallel Cyclic Redundancy Check (CRC) circuit, which is most widely adopted for error detection A new heuristic algorithm is developed to find as many shared terms as possible, thus eventually to minimize the number and level of the exclusive-or logic blocks in parallel CRC circuits. 16-bit and 32-bit CRC generators are designed with different types of Programmable Logic Devices, and it has been found that our new algorithm and architecture significantly reduce the delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4B
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• pp.257-269
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• 2003

S(Synchrous)-DMT(Discrete Multi Tone) is an emerging cable modem technology applicable to the upstream channel for high speed multimedia communication. In this paper we analyze the transmitting and receiving process of S-DMT scheme and derive bit error probability of S-DMT scheme in the $\varepsilon$-mixture impulse noise model which appropriately reflects impulse noise model which approproately reflects impulse noise characteristics of upstream channel. The analysis results show a good match with the simulation results. We also compare Eb/No gain performance of S-DMT with TDMA in 16-, 32-, 64-QAM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.26-34
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• 2002

Mobile telecommunication systems such as IS-95 and IMT-2000 employ frame based communication using frames up to 20 msec in length and the receiving end has to store the whole frome before it is being processed. The size of the frame buffer ofter dominates those of the processing unit such as soft decision Viterbi decoder. The frame buffer for IMT-2000, for example, has to be increased 80 times as large as that of IS-95. One of the parameters deciding the number of bits in a frame will be obviously the number of bits in soft quantization. Start after striking space key 2 times. This paper has studied a new aspect of offset and quantization step size on BER performance and proposes a new 3-bit soft quantization algorithm which shows similar performance as that of 4-bit soft decision Viterbi receiver. The optimal offset values and step sizes for the other practical quantization levels ---16, 8, 4, 2--- have also been found. In addition, a new optimal symbol metric table has been devised which takes the accumulation value of various repeated signals and produces a rescaled 3-bit valu.tart after striking space key 2 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.4C
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• pp.362-369
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• 2007

APSK (Amplitude Phase Shift Keying) digital modulation is characterized by the circular positioning of the transmission symbols in the constellation diagram. Due to such structural characteristics, the peak-to-average power ratio of the APSK modulation is lower than that of the QAM (Quadrature Amplitude Modulation), and the amount of performance degradation over nonlinear channels can be mitigated. The APSK modulation scheme has recently been adopted as satellite communication system standards including the DVB-S2 (Digital Video Broadcasting - Satellite, Version 2). In this paper, a BER (Bit Error Rate) upper bound approximation formula is derived using the channel model with the output power saturation characteristics, and its accuracy is demonstrated. Using the derived formula, the input power level that minimizes the BER is determined. The optimized performance based on the radii ratio of the 16APSK constellation and the channel saturation level is also presented.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.11a
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• pp.575-579
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• 2000

유전자 알고리즘을 구현하기 위해서 전용 원칩 컴퓨터를 설계하였다. 유전자 알고리즘의 전용 원칩 컴퓨터는 16Bit CPU CORE와 유전자 알고리즘의 하드웨어로 구성되어 있다. 구현된 전용 원칩 컴퓨터는 기존이 하드웨어 GAP와 달리 메인 컴퓨터에 독립적으로 동작되며 멀티미디어 통신에 사용되는 비트 동기용 하드웨어를 생성시켜본 결과 효과적임을 알 수 있었다.

• Electronics and Telecommunications Trends
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• v.27 no.3
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• pp.101-109
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• 2012

아날로그 방송에서 디지털로 전환이 완료되는 시점에서 full-HD 방송을 넘어서 4K 궁극적으로는 8K까지 초고화질의 콘텐츠에 대한 요구가 증가하고 있고, 이를 만족하기 위한 기술개발 및 장비에 대한 관심이 증폭되고 있다. 초고화질은 보통 HD의 4배에서 16배의 해상도를 가지고 화소당 할당되는 비트수도 10~12비트를 할당한다. 초고선명화질의 콘텐츠는 기존 품질의 콘텐츠에서 제공할 수 없었던 실감성과 몰입감을 제공해주기 때문에 방송, 영화, 스포츠, 광고, 전시, 공연, 의료 등의 많은 분야에서 관련 기술개발이 요구되고 있다. 본고에서는 8K급 고품질 콘텐츠의 제작 및 유통, 상영과 관련하여 응용 분야인 UHDTV 및 디지털시네마와 디지털사이니지에 초점을 맞추어 기술 및 산업 동향을 고찰하고자 한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.157-159
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• 2016

3가지 마스터키 길이 128/192/256 비트를 지원하는 파이프라인 LEA(Lightweight Encryption Algorithm) 크립토 프로세서를 설계하였다. 높은 처리율을 얻기 위해 16개의 라운드 스테이지가 파이프라인 방식으로 동작하며, 각 라운드 스테이지는 128비트 데이터패스를 갖도록 설계하였다. 설계된 LEA 프로세서는 FPGA 구현을 통해 하드웨어 동작을 검증하였다. Xilinx ISE로 합성한 결과, 최대 동작주파수 122MHz로 동작하여 7.8Gbps의 성능을 갖는 것으로 평가되었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.6
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• pp.498-508
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• 1991

This thesis presents a performance analysis algorithm that estimates erro performance of individual links, at the bit level, in an end-to-end digital connection using the model of 3-statte MarKov chain. The link model proposed the burst error behavior of each individual link. It also presents a method to concateante several individual links and extract a model for end-to-end digital connection. This resulting end-to-end model can be used to calculate performance parameters such as bit error rate(BER) and block error(BLER) for any block size.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.820-822
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• 2005

We have designed a 32-bit microprocessor with fixed point digital signal processing functionality. This processor, combines both general-purpose microprocessor and digital signal processor functionality using the reduced instruction set computer design principles. It has functional units for arithmetic operation, digital signal processing and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline stucture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.247-252
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• 2005

Currently, the decoder receives a 16 bit channel input and restores an 8 bit data symbol in the DVD system. Such modulation code of DVD is the EFMplus code, and it is composed of a main table and a sub table. For reducing the size of the code table, this paper divided the code table into 3 groups and we implemented the decoder using this new code table. After all, this method enables us to reduce the size of ROM as reducing the total number of code from 1376 to 750.