• 정보보호학회논문지
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• 제20권1호
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• pp.17-31
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• 2010

VANET(Vehicular Ad hoc NETwork)에서 차량들은 일괄 확인(batch verification) 기법을 이용해 많은 수의 서명 메시지를 효율적으로 검증할 수 있다. 하지만 각 차량에서의 개별적인 일괄 확인은 네트워크 전체적으로 볼 때 불필요한 중복 검증을 발생시킨다. 이 문제를 해결하기 위해 RSU(Road Side Unit)가 노드를 대신해서 일괄 확인을 수행 할 수 있지만, 이 방법은 일괄 확인이 실패했을 경우 유효하지 않은 서명을 효율적으로 찾을 수 있는 방법이 추가적으로 필요하다. 본 논문에서는 분산 일괄 확인 시스템을 설계하기 위해 고려되어야하는 몇 가지 방법론에 대해서 분석하고 참여 차량이 작은 크기의 서명 집합을 분산해서 일괄 확인하는 효율적인 분산 일괄 확인 시스템을 제안한다. 제안하는 시스템에서 각 노드는 RSU에게 단순 일괄 확인 결과만을 보고하거나 식별한 유효하지 않은 서명들을 보고할 수 있으며 이를 수신한 RSU는 노드의 이 일괄 검증 결과 리포트를 이용하여 효율적으로 유효하지 않은 서명을 식별하여 배제할 수 있다.

• 한국의학물리학회지:의학물리
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• 제30권4호
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• pp.120-127
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• 2019

Purpose: This study was designed to evaluate the dosimetric performance of Mobius3D by comparison with an aSi-based electronic portal imaging device (EPID) and Octavius 4D, which are conventionally used for patient-specific prescription dose verification. Methods: The study was conducted using nine patients who were treated by volumetric modulated arc therapy. To evaluate the feasibility of Mobius3D for prescription dose verification, we compared the QA results of Mobius3D to an aSi-based EPID and the Octavius 4D dose verification methods. The first was the comparison of the Mobius3D verification phantom dose, and the second was to gamma index analysis. Results: The percentage differences between the calculated point dose and measurements from a PTW31010 ion chamber were 1.6%±1.3%, 2.0%±0.8%, and 1.2%±1.2%, using collapsed cone convolution, an analytical anisotropic algorithm, and the AcurosXB algorithm respectively. The average difference was found to be 1.6%±0.3%. Additionally, in the case of using the PTW31014 ion chamber, the corresponding results were 2.0%±1.4%, 2.4%±2.1%, and 1.6%±2.5%, showing an average agreement within 2.0%±0.3%. Considering all the criteria, the Mobius3D result showed that the percentage dose difference from the EPID was within 0.46%±0.34% on average, and the percentage dose difference from Octavius 4D was within 3.14%±2.85% on average. Conclusions: We conclude that Mobius3D can be used interchangeably with phantom-based dosimetry systems, which are commonly used as patient-specific prescription dose verification tools, especially under the conditions of 3%/3 mm and 95% pass rate.

• Nuclear Engineering and Technology
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• 제41권1호
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• pp.79-90
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• 2009

Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.

• Coupled systems mechanics
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• 제4권1호
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• pp.67-98
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• 2015

Numerical prediction of dynamic behavior of fully coupled saturated porous media is of great importance in many engineering problems. Specifically, static and dynamic response of soils - porous media with pores filled with fluid, such as air, water, etc. - can only be modeled properly using fully coupled approaches. Modeling and simulation of static and dynamic behavior of soils require significant Verification and Validation (V&V) procedures in order to build credibility and increase confidence in numerical results. By definition, Verification is essentially a mathematics issue and it provides evidence that the model is solved correctly, while Validation, being a physics issue, provides evidence that the right model is solved. This paper focuses on Verification procedure for fully coupled modeling and simulation of porous media. Therefore, a complete Solution Verification suite has been developed consisting of analytical solutions for both static and dynamic problems of porous media, in time domain. Verification for fully coupled modeling and simulation of porous media has been performed through comparison of the numerical solutions with the analytical ones. Modeling and simulation is based on the so called, u-p-U formulation. Of particular interest are numerical dispersion effects which determine the level of numerical accuracy. These effects are investigated in detail, in an effort to suggest a compromise between numerical error and computational cost.

• 한국콘텐츠학회논문지
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• 제2권1호
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• pp.39-45
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• 2002

고문헌이나 예술품에 대한 저작자의 진위 여부 판정은 문화재 관리 측면이나 소장자의 재산가치 평가를 위해 상당히 중요한 측면을 가지고 있다. 이를 위해 문화재청의 전문가들이 진위 판정을 행하고 있는데 이는 경제적 비용이 상당히 소요된다. 따라서 이를 컴퓨터에 의해자동으로 행하는 시스템의 개발에 대한 사회적 욕구가 증대하고 있는 실정이다. 본 논문에서는 이를 위해 작품의 경계 형태 분석에 의해 저작자의 진위 여부를 판정하는 시스템을 개발하고자 한El. 이는 진품 판정에서 생각할수 있는 여러 1띠 특징 벡터 중 우선적으로 중요한 특징 벡터하고 생각되기 때문이며 차후여러 가지 특징 벡터를 취합하여 저작자의 진위 판정을 종합적으로 행하는 시스템을 개발하고자 한다. 최종적으로 본 논문의 유용성을 실험에 의해 입증코자 한다.

• 대한전자공학회논문지TC
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• 제46권1호
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• pp.89-93
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• 2009

본 논문은 에너지 검출기에 시간 지연 장치를 채택하여 복수번의 확인 과정을 갖는 향상된 스펙트럼 검출기에서 센싱 시간에 따른 성능의 영향을 알아본다. SNR은 1dB, 그리고 오보 확률은 0.1로 고정하고 3, 60, 100km/h의 다양한 이동 속도를 고려한 스즈키 채널 하에서 시뮬레이션을 통해 센싱 성능을 고찰하고 이를 기존의 에너지 검출기의 경우와 비교한다.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.204-207
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• 2000

Verification is one of the most critical and time-consuming tasks in today's design process. This paper describes the basic idea of Co-verification and the environment setup for the design of DVD Servo with TeakLite DSP core by using Seamless CVE, Hardware/software Co-verification too1.

• 한국초등과학교육학회지:초등과학교육
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• 제34권1호
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• pp.95-108
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• 2015

Studies showed that elementary school students had difficulties in the idea generation for creative problem solving, and they were also not to go through with the verification process for selecting idea. Thus, it may be more effective to provide an actualized idea generation and verification methods. In this study, we developed the creativity problem solving program with the attribute listing and PMI skills in the idea generation and verification stages respectively and applied it to six groups consisting of 5th elementary school students. We analyzed the creativity and the verbal interactions among the students at the level of interaction units. The analyses of the results revealed that the problem solving program with the creative thinking skills had significant effects on the fluency and originality that were sub-elements consisting creativity. In the analyses of interaction unit, the frequencies of the 'making suggestion' at the idea generation stage were high. And at the idea verification stage, the frequencies of the 'making suggestion' and 'receiving opinion' were high. Educational implications of these findings were discussed.

• 한국멀티미디어학회논문지
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• 제9권12호
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• pp.1607-1616
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• 2006

The growing market of multimedia and digital signal processing requires significant data-path portions of SoCs. However, the common models for verification are not suitable for SoCs. A novel model--WGL (Weighted Generalized List) is proposed, which is based on the general-list decomposition of polynomials, with three different weights and manipulation rules introduced to effect node sharing and the canonicity. Timing parameters and operations on them are also considered. Examples show the word-level WGL is the only model to linearly represent the common word-level functions and the bit-level WGL is especially suitable for arithmetic intensive circuits. The model is proved to be a uniform and efficient model for both bit-level and word-level functions. Then Based on the WGL model, a backward-construction logic-verification approach is presented, which reduces time and space complexity for multipliers to polynomial complexity(time complexity is less than $O(n^{3.6})$ and space complexity is less than $O(n^{1.5})$) without hierarchical partitioning. Finally, a construction methodology of word-level polynomials is also presented in order to implement complex high-level verification, which combines order computation and coefficient solving, and adopts an efficient backward approach. The construction complexity is much less than the existing ones, e.g. the construction time for multipliers grows at the power of less than 1.6 in the size of the input word without increasing the maximal space required. The WGL model and the verification methods based on WGL show their theoretical and applicable significance in SoC design.