• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.81-88
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• 2004

In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188by1e) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.10
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• pp.1005-1016
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• 2002

In this paper, a 2 GHz tapered shape of multiport power divider/combiner modified from the model published by [10] and adopted PBG(Photonic Band Gap) structure is proposed. Parameters determining electrical property of the circuit structure have been analyzed by HFSS simulation. For input matching, balance of output signals and phase linearity at each output port, one circular hole has been etched out on the circuit surface. 1:2 and 1:3 power dividers/combiners designed by this study have been compared with the same circuits designed by the method of [10] in terms of S-parameters. As a result, it has been found that tile modified structure and PBG of power divider/combiner have improved return loss more than 20 dB and another 18 dB. respectively, at 2 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.54-61
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• 2001

A fully on-chip open-drain CMOS output driver was designed for high bandwidth DRAMs, such that its output voltage swing was insensitive to the variations of temperature and supply voltage. An auto refresh signal was used to update the contents of the current control register, which determined the transistors to be turned-on among the six binary-weighted transistors of an output driver. Because the auto refresh signal is available in DRAM chips, the output driver of this work does not require any external signals to update the current control register. During the time interval while the update is in progress, a negative feedback loop is formed to maintain the low level output voltage ($V_OL$) to be equal to the reference voltage ($V_{OL.ref}$) which is generated by a low-voltage bandgap reference circuit. Test results showed the successful operation at the data rate up to 1Gb/s. The worst-case variations of $V_{OL.ref}$ and $V_OL$ of the proposed output driver were measured to be 2.5% and 7.5% respectively within a temperature range of $20^{\circ}C$ to $90^{\circ}C$ and a supply voltage range of 2.25V to 2.75V, while the worst-case variation of $V_OL$ of the conventional output driver was measured to be 24% at the same temperature and supply voltage ranges.

• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.224-227
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• 2000

지금까지 멀티레벨 컨버터 및 인버터에 적용되어온 기존의 스너버는 턴온 스너버로 RLD 스너버 턴오프 스너버로 RCD 스너버를 사용하였으나 이들 RCD/RLD는 많은 소자를 필요로하며 스위칭시의 overvoltage와 스너버 손실이 큰 단점을 지니고 있다. 이와같은 문제점을 해결하기 위해 본 논문에서는 Diode-clamped 4-레벨 컨버터 및 인버터를 위한 새로운 스너버를 제안한다. 새로 제안하는 스너버는 Basic snubber unit로 특성이 좋은 Undeland 스너버와 수정된 RCD/RLD 스너버를 사용한다. 따라서 제안하는 스너버는 Undeland 스너버와 McMuray 스너버가 갖고 있는 특성 즉 사용소자의 수의 감소 과전압의 감소 스너버 손실의 감소 등과 좋은 특성을 지니고 있다 또한 본 논문에서 제안하는 4-레벨 컨버터 및 인버터를 위한 스너버 회로를 구성하는 방법은 다른 레벨의 멀티레벨 컨버터 및 인버터에도 적용가능하다,

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2634-2636
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• 2004

다목적실용위성2호의 위성 본체시스템에는 지상과 연락을 담당하는 주 컴퓨터인 OBC, 위성의 자세를 제어를 위한 원격구동장치인 RDU 그리고 위성의 전원분배를 제어장치인 ECU인 3개의 동일 프로세서(386)가 탑재되어 각 담당 임무를 수행하는 분산형 구조를 갖고 있다. 각 프로세서는 EEPROM과 SRAM 데이터 메모리를 갖고 있는데 전원 리셋이 일어나면 모든 프로그램은 EEPROM에서 SRAM으로 복사되어 운영 프로그램이 실행하도록 되어 있다. 그러나 SRAM은 우주환경에서 위성체는 방사선에 노출되어 손상을 입을 때 SEU이 발생되어 정보가 왜곡되거나 상실되는 문제를 갖고 있다. 그러므로 본 논문에서는 변형된 해밍코드 기법을 이용하여 데이터를 수신하는 곳에서 에러를 검출 및 수정하는 디지털 회로 설계방법을 기술하고자 한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.11a
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• pp.29-32
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• 2012

하드웨어 Trojan은 악의적인 목적으로 전자 회로망에 수정을 가한 회로로, Trojan 설계자의 목적에 따라 특정 환경에서 동작(Trigger) 되어 전체 시스템에 심각한 보안문제를 초래할 수 있다. 일반적으로 Trojan은 동작 시 시스템의 방화벽이나 보안 장치 등의 시스템 일부를 하드웨어적으로 무력화 시켜 제 기능을 상실시키며 심각한 경우 시스템 전반에 걸쳐 모든 기능을 마비시킬 가능성이 있다. 본 연구에서는 군사 시설과 같이 고도의 보안 및 정확성이 요구되는 시스템 분야에서 신뢰성 향상에 초점을 두고, 서로 다른 프로세서에서 같은 연산을 처리하여 이를 비교할 수 있는 Vote Counter를 탑재한 이질 시스템(Heterogeneous system)을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1038-1045
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• 1994

In this paper, algorithm and built-in test circuit for testing all PSF(Pattern Sensitive Fault) occuring in CAM(Content Addressable Memory) are proposed. That is, built-in test circuit that uses minimum additional circuit without external equipment is designed. Additional circuit consist`s of parallel comparator, error detector, and modified decoder for parallel testing. Besides, the study on eulerian path for effectiv test pattern is carried out simultaneously. Consequently, using proposed algorithm, we can test all contents of CAM with 325+2b(b:number of bits) operations regardless of number of words. The area occupied by test circuit is about 7.5% of total circuit area.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1331-1336
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• 2014

In this study, we have implemented a PAM(Power Amplifier Module) with 25W output power using by cooperate divider/Combiner circuit in X-band to minimize combine loss on a Al2O3 substrate. The PAM(Power Amplifier Module) is consisted of MMIC and 10way traveling wave divider/Combiner with proposed structure what have showed that 45.2dBm output power, 16dB gain, PAE 26 % and 17dBc@44dBm IMD3 characteristics. This combine/divider structure can be used when multistage passive divider and combiner needs. especially, power amplifier with very compact size.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.6
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• pp.27-27
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• 2002

In this paper, the LPA(Linear Power Amplifier) using new analog feedforward linearizer for IMT-2000 frequency band(2110MHz∼2170MHz) is proposed and fabricated. The designed analog feedforward linearizer system possessing the characteristics of stable operation for input power variation is simple structure and small size. When two-tones in IMT-2000 frequency band are applied to an amplifier, this LPA have the average output power is about 30W and the IMD value is below about 60dBc without correcting the circuit. In camparision with an amplifier without feedforward system at the same output power, the supposed analog feedforward linear amplifier posseses improved the IMD characteristics of over 23dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.6
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• pp.285-291
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• 2002

In this paper, the LPA(Linear Power Amplifier) using new analog feedforward linearizer for IMT-2000 frequency band(2110MHz∼2170MHz) is proposed and fabricated. The designed analog feedforward linearizer system possessing the characteristics of stable operation for input power variation is simple structure and small size. When two-tones in IMT-2000 frequency band are applied to an amplifier, this LPA have the average output power is about 30W and the IMD value is below about 60dBc without correcting the circuit. In camparision with an amplifier without feedforward system at the same output power, the supposed analog feedforward linear amplifier posseses improved the IMD characteristics of over 23dB.